IDesignSpecTM (IDS) : Executable Design Specification Tool

See short demo video |  Download Brochure | Frequently Asked Questions

 

IDesignSpecTM is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec's PATENTED technology improves engineer's productivity and design quality.

 

Write once, generate all

 

Key Benefits

 

  • Automatically Verify all addressable registers in the design
  • Create synthesizable code for registers
  • Get a jump start for Device Driver, Firmware and application software development
  • Automatically create documentation for customers and Tech-Pubs
  • Improves productivity of engineers and quality of results.
  • Supports Architecture, Design, Verification, Diagnostics, Firmware, Application Software and Documentation groups.

 

Key Features

  • Easy to use Plugin for all popular Editors.  No need for any new tool, and no new language to learn.
  • Transformations possible out of the box:
    • Verilog, VHDL synthesizable design code for industry standard bus protocols (AMBA-AHB, AVALON, and Proprietary)
    • Test bench files for OVM, VMM, UVM, eRM (vr_ad)
    • C header files, and C++ Class files for Firmware and Device Drivers
    • HTML and PDF documentation
    • SystemC, SystemVerilog based Verification code (based on UVM, OVM and VMM methodology)
    • IP-XACT output conforming to Spirit Consortium
    • SystemRDL standard output
  • Imports : IP-XACT, SystemRDL, XML, CSV
  • Register data stored in native editor format, not locked to Agnisys. Provides complete register data portability.
  • Extensible: User defined transformations are possible using Tcl or XSLT.

 

IDesignSpec is available in two forms

1)    As a plug-in for all popular editors (MS Word 2003, 2007, 2010, MS Excel 2007, OpenOffice.org and FrameMaker®)
2)    As a command line utility for Windows®, Linux and Solaris platforms

Unique customer engagement model

Agnisys has a unique engagement model, in that its support team helps the customer bring their existing register specs into IDesignSpec. We create Tcl or XSLT scripts to generate the exact output that works in the customer’s existing flow. Without spending much time customers are able to evaluate the tool and the improved work flow. Customers are not locked into the Agnisys file format since the files are stored in the native document editor, under complete control of the user.

 

More details about UVM Registers

Automatic generation of Register Model for VMM using IDesignSpec

How to use UVM Registers?

Download IDesignSpec Brochure

IDesignSpec White Paper

OVM IDesignSpec White Paper

Automatic Generation of OVM/UVM registers (DAC 2010)

Strong Foundations for Engineering with IDesignSpec

 

Next Steps

> Watch a short introductory demo video.

> For a product evaluation click here.

> To try IDesignSpec on the Xuropa cloud click here. (Note: A Xuropa registration will be required)

> Click on Live Chat now. A Live Chat button will be available if support personnel are available to man it.


IDS Testimonial

A very positive experience so far.

Inphi Corporation

I really like your tool as it is a great time saver, and excellent utility for bridging reqmts and design... and it is priced well.

Raytheon

 

Thanks a lot! Great tool by the way.

JPL NASA

 

It (IDSBatch, IDSExcel) works like a charm! Thank you so much for the great assistance... Integration with R&D was smooth.

Alon Shtepel, Professional Services Group Leader, Discretix

 

 

I’ve been very happy with iDesignSpec (IDSWord). No real issues at this point. … We’re about to do some additional IP development in the next 6 months so I’ll provide more feedback when I get back into the tool. I’ve successfully used it in 2 IP blocks so far.

An Engineer in the Defense Sector

 

"IDesignSpec greatly helped us in creating and maintaining executable specs for blocks in our SoC. It saved a lot of manual efforts by automatically generating the required OVM register package code for each of these blocks. With this we were able to efficiently automate and complete all our register verification tests in a short time. It also allowed easy use of the register package for higher level checks performed as part of the top level verification of the SoC."

Santosh Sarma, Wipro Technologies Ltd.

 

"We are pleased that Agnisys has made available the first automatic generation of OVM 1.0 register package validated to run on the Questa® functional verification platform. As a highly active member of the Mentor Questa Vanguard Partnership program, Agnisys works with us to improve design and verification productivity"

Dennis Brophy, Director of Strategic Business Development, Mentor Graphics