DAC May Be Virtual, but Our New Products Are Not
Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time
Read moreSmart Assembly of SoC Designs
System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the challenges faced
Read moreThree Steps to Set Up a RISC-V SoC UVM Testbench
Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides
Read moreAutomation of the UVM Register Abstraction Layer
A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the
Read moreDoing What We Can in Challenging Times
Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as
Read moreCorrect-By-Construction SystemVerilog UVM Testbenches
Modern RTL design verification (DV) environments are both very powerful and very complex. They include advanced simulation testbenches plus support for formal verification, virtual prototypes, and emulation technology. Even within
Read more9 Ways Commercial Register Generation Tools Provide Greater Value Than Custom Scripts
July 17, 2014
Uttam Sarkar
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