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Begin Initialization Sequence – 10, 9, 8, …

7

Dec, 2012

Begin Initialization Sequence – 10, 9, 8, …

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OK rockets are not taking off yet, but we are excited to launch a new capability for our IDesignSpec suite of tools. After years of working on Registers and Memory map for hardware we are taking the next giant leap for us and a small step for engineers worldwide (drum roll please ... :)) SEQUENCES.

Yes! we have added the ability for users to create sequences in the specification document itself. So whats new, you might ask. Here is what is new - as with registers and memories, these sequences are added in a manner which enables us to pick out the information and transform it into code for Firmware, Software, and even Verification code right from the specification document.

Now that's automation I like.

With the traditional IDesignSpec, we have been able to bring Hardware, Verification and Firmware engineers together and share details of the Registers and Memory space for embedded designs. Our experience with customers enabled us to leverage this body of knowledge and take the next step. Sequences have been traditionally captured in a specification document in a non structured way, and as with other parts of the spec, this information is sent over to different groups which (mis)interpret and manually code it in a way suitable for their needs, often introducing hard to find bugs.

With the new capability, you create the sequence and get firmware, verification (UVM etc.) code from it. These sequences can be initialization, bring up, configuration, and others related to the core functionality of the device.

The high level sequences in the spec are converted into low-level C-code for firmware and SystemVerilog UVM code for verification. You can even put in properties to control reads/writes thru front or back-door.

We look forward to hearing from you about this new functionality, that we are calling ...

 

(sorry no awards for guessing this one ...)

 

ISequenceSpec

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