August 11, 2019

Repurposing von Neumann Architecture with SRAM-based Register Files

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big data the entire industry has put a spotlight on its limitations. Since massive amounts of data need to travel back and forth between the CPU and memory, the resulting latency and power consumption became major issues. One of the powerful ...

May 20, 2019

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the ...

April 15, 2019

EDA Is Advancing – but Where Are the Women?

By Ishanee Bajpai – Senior Marketing Executive, Agnisys 1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.  As the ...

March 26, 2019

Setting the Stage for the Next Abstraction

By Louie De Luna, Agnisys Chief Product Evangelist As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to schematics to ...

February 17, 2019

Register Automation using Machine Learning

By Louie De Luna, Agnisys Director of Sales and Marketing Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into ...

May 27, 2016

It’s All In The Sequence

Whether dealing with SoCs or a disaster in space, determining the correct set of steps is vital. No project team wants a “Houston, we have a problem,” moment. And yet, they happen all too frequently, even though there ...

May 5, 2016

Making Way For Register Specification Software

While more registers means more functionality and configurability, more is not always better. No one gives much thought to the heating, ventilation and air conditioning registers in the house–typically, two in each ...

April 11, 2016

The Ultimate Shift Left

Important observations from Einstein and New England’s ice traders.. Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several ...

December 30, 2015

2015 Year End review – DV Challenges

Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget – new partnership. It would be unfair to say ...

September 21, 2015

Does UVM sometimes make you feel stupid?

Somewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity. As the saying goes, the faint of heart need not attempt UVM based verification. But what makes it so ...

July 22, 2015

Questa® VIP validates IDesignSpec generated IP

In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it has different channels for ...

February 5, 2014

DVCON 2014: Strong Focus on both, Design & Verification

Here we go! The Design and Verification Conference (DVCON 2014) is round the corner. Make sure you register for the event which has been one of the premier conferences for IC design and verification engineers. This ...

December 7, 2012

Begin Initialization Sequence – 10, 9, 8, …

Launching new capability to specify Sequences in IDesignSpec