February 22, 2024

Empowering Designers: The User-Friendly World of IDesignSpec GUI Options

Simplify specs with Agnisys IDesignSpec™. Choose user-friendly GUIs for efficient design and enhanced productivity.

[Specification Automation]
February 12, 2024

Too Many Iterations? How to Avoid Three Common Problems in Semiconductor Design

Developing semiconductor intellectual property (IP), system-on-chip (SoC) designs, and complete systems is enormously challenging.

Specification Automation
January 24, 2024

Six Smart Ways Specification Automation Reduces Register Implementation Time

Six advantages of specification automation that overpower manual register implementation.

Chip Block
January 15, 2024

Bridging the Gap: Agnisys Contribution to Specification Automation

Unlock SoC design excellence with Agnisys advanced automation. Streamline register specs, expedite projects, and elevate semiconductor standards seamlessly.

IDesignSpec Data Flow Diagram
January 8, 2024

Agnisys: Pioneers in Specification Automation and Beyond

Agnisys revolutionizes electronic design with IDesignSpec Suite, automating RTL, code, and verification for safety-compliant collaboration.

IDS-Validate
December 8, 2023

Getting Started with IDS-Validate

Master the crucial steps in setting up IDS-Validate with RISC-V toolchains, Veer core RTL, and UVM. Collaborate with Agnisys for streamlined simulation and firmware testing.

December 1, 2023

Three Smart Steps to Quickly Test a Register Map for Your Entire SoC

Accelerate SoC development with three smart steps to swiftly test your entire Register Map. Streamline verification processes, enhance efficiency, and ensure seamless integration with our proven methodology for ...

November 28, 2023

Custom IP Design and AI-Based Verification

Experience the prowess of custom IP design and AI verification through Agnisys' IDS-IPGen. Streamline your chip development for optimal results.

Streamline SOC Verification with Agnisys: UVM Testbench & More
October 6, 2023

Integration is Key for the Adoption of Specification Automation

Discover the power of specification automation at Agnisys. From UVM testbench to SystemRDL to C/C++, integrate seamlessly for efficient SOC verification.

Reduce Errors with Automation
April 25, 2023

How to Improve Your IC Design and Reduce Errors with Automation Solutions from Agnisys

How to improve your IC and IP designs and reduce errors with industry-leading executable specification automation solutions from Agnisys.

What’s Next in Specification Automation
April 25, 2022

What’s New and What’s Next in Specification Automation?

SoC design needs automatic generation of hardware, software, testbenches, tests, and documentation from executable specifications.

New Methods For Faster Development
December 9, 2019

Adopting New Methods For Faster Development Of RISC-V based SoCs

Explore Accelerated RISC-V SoC Development in Our Blogs. Stay Ahead in Semiconductor Tech. Unleash Innovation! Accelerated RISC-V SoC Development.

Repurposing von Neumann Architecture with SRAM-based Register Files
August 11, 2019

Repurposing von Neumann Architecture with SRAM-based Register File

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades.

Not your Average UVM Testbench Generator
May 20, 2019

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

Get ready to witness an extraordinary UVM testbench generator at DAC 2019. Experience innovation like never before, only at Agnisys.

Setting the Stage for the Next Abstraction
March 26, 2019

Setting the Stage for the Next Abstraction

Explore Agnisys' groundbreaking approach in setting the stage for advanced abstraction. Discover how our solutions redefine the future of technology.

Register Automation using Machine Learning
February 17, 2019

Register Automation using Machine Learning

By Louie De Luna, Agnisys Director of Sales and Marketing Right after Google’s AlphaGo system defeated a human Go world champion in 2015. Visit now.

Top 2018 Agnisys Resources
December 17, 2018

Top 2018 Agnisys Resources

Discover the top 2018 Agnisys resources for cutting-edge insights and solutions in the field of technology. Explore now!

Automating Register Verification
December 3, 2018

Automating Register Verification with 100% Functional Coverage

By Louie de Luna, Agnisys Director of Sales and Marketing UVM has certainly improved reusability of verification environments for SoC projects. Learn more

What ARE the Root Causes of Functional Flaws?
October 30, 2018

What ARE the Root Causes of Functional Flaws?

Explore the root causes of functional flaws in this insightful blog by Agnisys. Gain a deeper understanding of the challenges and solutions.

Out of the Office
August 24, 2018

Out of the Office – Lessons from a client visit in Edinburgh

Discover the magic of Edinburgh, Scotland's capital, through a professional's perspective. Explore its beauty, culture, and reflection on meaningful trip.

It’s All In The Sequence
May 27, 2016

It’s All In The Sequence

Innovative Design Automation Tools: Streamline complex sequences for SoCs, ensuring precision and efficiency. Learn from Apollo 13's lesson.

Making Way For Register Specification Software
May 5, 2016

Making Way For Register Specification Software

Discover how Agnisys reshapes hardware development with cutting-edge Register Specification Software. Elevate your electronics innovation today!

The Ultimate Shift Left
April 11, 2016

The Ultimate Shift Left

Einstein's wisdom meets semiconductor innovation: Shift left with specification-driven design for flawless results. Explore Agnisys' solutions.

2015 Year End review
December 30, 2015

2015 Year End review – DV Challenges

Agnisys reflects on a successful 2015, highlighting partnerships, events, and product innovations in the semiconductor industry.

Musings from ARM TechCon Santa Clara 2015
December 9, 2015

Musings from ARM TechCon Santa Clara 2015

Explore Agnisys' debut at ARM TechCon, connecting with SoC engineers, showcasing innovative technology, and addressing industry pain points.

Does UVM sometimes make you feel stupid?
September 21, 2015

Does UVM sometimes make you feel stupid?

Don't feel 'stupid' with UVM. Find solutions to common challenges and elevate your understanding. Dive in with Agnisys for insights.

IDesignSpec generated IP
July 22, 2015

Questa® VIP validates IDesignSpec generated IP

Discover how Questa VIP (QVIP) from Mentor Graphics simplifies AMBA AXI4Lite bus protocol verification, saving time and ensuring high-quality .

Semiconductor Data Sheet Automation
July 11, 2015

Semiconductor Data Sheet Automation – Just The Way You Want It

Transform semiconductor data sheet processes with Agnisys – your key to efficient automation tailored to your specifications. Elevate precision seamlessly.

Electronic Design Automation Trade Show Update – 52DAC
June 27, 2015

Electronic Design Automation Trade Show Update – 52DAC

Stay informed on the latest innovations in electronic design at the 52nd DAC trade show. Explore cutting-edge EDA solutions and trends.

Create Complex Registers in IDesignSpec
May 28, 2015

How To Create Complex Registers in IDesignSpec

Discover efficient strategies for managing intricate register designs using Agnisys iDesignSpec, streamlining your development process

Semiconductor Register Specification
March 4, 2015

Semiconductor Register Specification: Shadow of a Shadow

Explore challenges in semiconductor register specification & solutions like IDesignSpec tool for versatile register data management discussed at DVCon.

IDesignSpec for The TOTEM Experiment Project
December 10, 2014

CERN Selects IDesignSpec for The TOTEM Project at the Hadron Collider

The Large Hadron Collider (LHC) at CERN is the world's largest and most powerful particle accelerator. They have adopted Agnisys producs.

DVCon Europe Needs Automatic Register Verification and Generation
October 30, 2014

DVCon Europe Needs Automatic Register Verification and Generation

Explore the need for automatic register verification generation at DVCon Europe. Dive into our insightful blog for innovative solutions. Learn more now!

DVCon India takes off
September 26, 2014

DVCon India takes off!

Explore the highlights of DVCon India - a premier conference on design and verification, featuring cutting-edge insights and innovation. Learn more!

Getting Ready for DVCon India 2014
September 24, 2014

Getting Ready for DVCon India 2014

Join us for the exciting launch of ARV at DVCon India 2023! Explore innovative products and engage with industry leaders.

What Every Engineer Should Know About SoC Register Generation
July 17, 2014

What Every Engineer Should Know About SoC Register Generation

Explore crucial insights into SoC register generation for engineers. Stay informed on key processes and best practices with Agnisys, your trusted expert.

Reduce SV/UVM Implementation Time
July 17, 2014

5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

Discover time-saving strategies with Agnisys' powerful register generation tools, reshaping SystemVerilog UVM implementation timelines

System On Chip Design Challenges Addressed by Agnisys
June 4, 2014

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

Discover how Agnisys products tackle System on Chip design challenges at DAC Day 2. Stay updated on cutting-edge semiconductor solutions.

EDA Companies must Collaborate or Die
September 10, 2013

EDA Companies must Collaborate or Die

Discover why collaboration is imperative for EDA companies to thrive in a rapidly evolving industry. Explore insights on the Agnisys blog.

Using IVerifySpec to test IDesignSpec
May 28, 2013

Using IVerifySpec to test IDesignSpec

IDesignSpec generates several outputs from a single spec, evolving into an executable spec tool for digital design. Here's how we ensure its quality.

Complete Register Design Automation
May 28, 2013

IDesignSpec Provides Complete Register Design Automation

Discover iDesignSpec, the ultimate register design automation solution. Streamline your semiconductor design process with Agnisys. Learn more now!

Agnisys makes Design Verification process extremely efficient
May 28, 2013

Agnisys makes Design Verification process extremely efficient!

Discover how Agnisys revolutionizes design verification, enhancing efficiency in the process. Explore our blog for insights and solutions.

Begin Initialization Sequence
December 7, 2012

Begin Initialization Sequence – 10, 9, 8, …

Launching new capability to specify Sequences in IDesignSpec

#47DAC musings
June 19, 2010

#47DAC musings

Going to DAC had a boosting effect on us.

Great turnout at the Design Automation Conference
July 28, 2009

Great turnout at the Design Automation Conference

Exciting start at DAC! Positive vibes, innovative products, and unexpected connections. Join the conversation in the world of tech.

First sale is always sweet
June 17, 2009

First sale is always sweet!

We have a customer who sees the value that IDesignSpec brings for his company. We are indeed thankful to them for trusting our technology. Sign up now.

Is cheap EDA tool an oxymoron?
May 25, 2009

Is cheap EDA tool an oxymoron?

Adapting EDA software pricing amidst economic changes: Balancing affordability and industry needs for semiconductor success.

Why is it difficult to make your first EDA tool sale?
April 25, 2009

Why is it difficult to make your first EDA tool sale?

Revolutionary EDA tool saves you time & money. No costly sales teams or consultants. Discover affordable innovation!

IDesignSpec
April 24, 2009

IDesignSpec: An Engineering tool with a difference.

Transform your engineering workflow with IDesignSpec: Effortlessly convert functional specs into register descriptions, unlock automation's full potential.