Functional Safety and Security in Embedded Systems
Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect of our lives that is not controlled, monitored, or connected by
Read moreA Unified Flow for Embedded Systems Development
Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual
Read moreAutomatic Handling of Register Clock Domain Crossings
Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their predecessors who
Read moreSpecification-Driven UVM Testbench Generation
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world
Read moreThe Next Generation of Register, Sequence, and SoC Automation
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification,
Read moreAutomating IP Design and Verification
In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators
Read moreDAC May Be Virtual, but Our New Products Are Not
Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time
Read moreSmart Assembly of SoC Designs
System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the challenges faced
Read moreThree Steps to Set Up a RISC-V SoC UVM Testbench
Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides
Read moreAutomation of the UVM Register Abstraction Layer
A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the
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