Winding Up an Eventful Year
As we close in on the final days of 2021, I can’t help but think back over the events of the year and offer a few observations. At the front
Read moreWelcome Back to DAC – in Person – in San Francisco
Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC). It’s the stimulating combination of a highly technical conference
Read moreAn Update on Functional Safety and ISO 26262
Just about a year ago, I published a blog post about the emerging need for better functional safety and security in a wide range of electronic products. We recently
Read moreSystem-Level Register and Sequence Verification with UVM and Embedded C/C++
As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate the SystemVerilog RTL design, Universal Verification Methodology (UVM) testbench models
Read moreSpecification Automation for Formal Verification
I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series on specification automation. We’re focusing on the requirements for
Read moreAutomating Your Documentation Flow
In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property
Read moreSpecification Automation for Designers
If there’s one good thing to emerge amid all the challenges of the last year and a half, it’s improved technology for remote learning. On-line talks, webinars, and podcasts are
Read moreSetting a High Standard for Standards-Based IP
In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not
Read moreAutomating the UVM Register Abstraction Layer (RAL)
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a
Read moreAutomating IP and SoC Development
The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed in my last post, we held our first Agnisys
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