It’s All In The Sequence
The Beginning
Identifying the challenges in moving from a static spec to a live one.
We all want our creations to transcend time. Our products, our
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2015 Year End review – DV Challenges
Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget
Read moreMusings from ARM TechCon Santa Clara 2015
The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in Agnisys. Since it was our first foray into ARM TechCon,
Read moreDoes UVM sometimes make you feel stupid?
Somewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity.
As the saying goes, the faint of heart
Read moreQuesta® VIP validates IDesignSpec generated IP
In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it
Read moreHow To Create Complex Registers in IDesignSpec
We talk about creation of complex registers in IDesignSpec, generation of their suitable RTL and UVM models. The Software addressable registers in your design
Read moreSemiconductor Register Specification: Shadow of a Shadow
So we have been working in the register specification space for a long time. We came out with the IDesignSpec tool around 2010. Five years of constant refinement and evolution
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