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UVM | Agnisys

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  • Archive by Category "UVM"

Creating Test Sequences for RISC-V Cores and SoCs

October 7, 2019 marketing@agnisys.com 0

By Louie De Luna, Agnisys Chief Product Evangelist The idea of an open-source CPU core was virtually unheard-of ten years ago - let alone using it for commercial applications. The CPU

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Not your Average UVM Testbench Generator – Unveiling at DAC 2019

May 20, 2019 marketing@agnisys.com 0

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t

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Top 2018 Agnisys Resources

December 17, 2018 marketing@agnisys.com 0

Every year we take a look back at the resources we've created to determine what you've found most useful. We invite you to take a look below at our top

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Automating Register Verification with 100% Functional Coverage

December 3, 2018 marketing@agnisys.com 0

 By Louie de Luna, Agnisys Director of Sales and Marketing UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics industry. Since

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Recent Posts
  • Tool Qualification Kit for Functional Safety Compliance
  • Tight Generator Interface support in SoC-E
  • Chip-in-Chip support for multiple input format
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