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CERN Selects IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider

CERN Selects IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider

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The Large Hadron Collider (LHC) at CERN is the worlds largest and most powerful particle accelerator. This research facility enables some of the most advanced scientific experiments. 

CERN Large Hadron Collider

The TOTEM experiment is dedicated to the precise measurement of the proton-proton interaction cross section

Most of the LHC experiments are on a grand scale, however, TOTEM's (TOTal cross section, Elastic scattering and diffraction dissociation Measurement at the LHC)'s characteristic is its extension over 440 meters. TOTEM's physics program is dedicated to the precise measurement of the proton-proton interaction cross section, as well as to the in-depth study of the proton structure which is still poorly understood. 

Why CERN selected IDesignSpec

CERN-IDesignSpec Success Story

Because of the advanced complexity of the TOTEM project, the team needed the ability to document the design registers and ensure the hardware code and the c-header register files matched and stayed synchronized as design changes occurred during the project. 

"IDesignSpec enabled TOTEM to improve efficiency of work time of three separate processes (to date): register specification, documentation and implementation are condensed to a single interaction with the tool saving time and eliminating errors."  Adrian Fiergolski - CERN

The Benefits Realized by CERN From Using IDesignSpec

In previous projects, when register changes would occur, it was very difficult to communicate the change accurately to the many team members.  As a result, as the hardware and software were integrated in the lab, the team would run into bugs that would take a long while to identify and then resolve.  Even though one would think register definition is a simple item, errors in implementing them caused significant project delays.  Once the team implemented IDesignSpec and used the HDL register code and C-Header file automatic code generation capability, the errors in implementing registers in the hardware and software were eliminated. 

“With IDesignSpec, the product was very easy to use and development follows naturally after requirements and documentation; consistency between firmware and software code is guaranteed!”       Michele Quinto of CERN

To learn more about Agnisys' IDesignSpec please view an online demonstration or request an evaluation to experience its capabilities.

 IDesignSpec Demonstration request   Evaluate a full version of IDesignSpec - System Verilog Code Generation for UVM Verification