IDesignSpec™ supports properties like wr_stb_stages and addr_decode_stages at the block/register level that gives the flexibility of adding/inserting delays in the read-back path and address decode logic in the generated RTL. The main advantage of introducing such delays at various stages is to meet timing requirements in case the number of registers is large, and the clock frequency is high.

Adding these properties also ensures the consistency of the incoming bus data during the course of the inserted delays. With the delays added in the write strobe stages along with address decode logic (with the properties- wr_stb_stages and addr_decode_stages respectively), the data received is held at the original clock tick until the delayed clock cycle when the address is finally decoded. This is ensured with the help of a default sequential logic that is in sync with the data slicing logic of the properties ‘addr_decode_stages’ and ‘wr_stb_stages’ which must be used together with the same property value to maintain data consistency.

Fig A:  wave-diagram of data transmission on  adding delays


Output Verilog

 . . .

 . . .

// wr_data Stages

    always @(posedge clk)  begin

    if (!reset_l)


            Reg1_wr_data0 <= ‘b0;

            Reg1_wr_data1 <= ‘b0;




            Reg1_wr_data0 <= wr_data;

            Reg1_wr_data1 <= Reg1_wr_data0;


end//end always

. . .

. . .


                    Adding delays/stages in the data transmission path is ensured with the consistency of data received from the register bus interface which is synchronized with the used delay stages properties (address decode stages, write strobe stages) resulting in a change in register data with the updated software data when the valid address is finally decoded.

-Yogita Koli

By NO Comment November 16, 2022

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