Developing and integrating IPs and device drivers with processor cores based on RISC-V is a daunting task that requires a lot of automation and expertise. In this presentation, we will discuss best-practices for design/verification of control/status registers (CSR) using template-based methodology. The design, firmware and verification teams can generate RTL, C/C++ Headers, UVM register model, Python and PDF from a golden specification. We will show how to capture the CSR programming sequences in pseudo-code and generate the sequence code in UVM, RISC-V ASM, C or SystemVerilog tasks that can be used for simulation, firmware, emulation and post-silicon validation. These sequences can also be used to support the wide range of RISC-V ISA bases and extensions.
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