1. Short workshop: IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!
    Date
    : Monday, February 28
    Time: 11:30 am – 12:30 pm PST
  2. Paper presentation: Automatic Translation of Natural Language to SystemVerilog Assertions
    Date : Tuesday, March 1
    Time : 15:00 pm – 17:00 pm PST
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