Visit Us at DVCon 2016
FEBRUARY 29 – MARCH 3, 2016
DoubleTree, San Jose
Welcome to our first event of the year – DVCon US 2016, San Jose, CA. We have lots of exciting work to show the attendees. Several new tools, and new features in existing tools.
Please stop by to see how we are implementing our mission of specification realization with automation.
We will be showing the following …
- Standard Compliant AMBA-AHB, APB and AXI supported RTL
- Set and modify of properties using TCL API at RunTime
- Verilog in two variants- 1995 and 2001 standard
- Synthesizable SystemC RTL
- Formal Assertions
Automatic Register Verification (ARV) : ARV helps to attain automatic coverage closure in register verification by verifying all kinds of register behaviours like all Software accesses , constrained random and also quirky behaviours like lock, shadow, alias, indirect access etc.
ISequenceSpec™ (ISS) : Portable Sequence is here already! ISequenceSpec enables users to describe sequences in a spreadsheet and create outputs with for various teams such as : Verification, Validation, Firmware and Software.
DVinsight™ (DVi) : DVi helps to reduce the learning curve of new DV engineers while accelerating error-free code development by the expert DV developer.
SoC Enterprise™ (SoCe): Just a sneak peek!
Monday, February 29 5:00 – 7:00pm
Tuesday, March 1 2:30 – 6:00pm
Wednesday, March 2 2:30 – 6:00pm