The Design Verification Conference and Exhibit (DVCon) is coming to Bangalore India on September 25th and 26th. Agnisys will exhibit at the conference in booth 9.
Visit Agnisys to see how semiconductor design and verification engineers can create the register map specification for their digital system once and automatically generate all of the required outputs with IDesignSpec™. If you are developing System Verilog UVM code then DVinsight can help accelerate your coding speed while reducing errors.
Don’t forget to attend these demonstrations at DVCon India
Don’t Forget to play Glory Games
This year at DVCon India try something different, participate is the Agnisys Glory Games. Playing the game is simple and the survivors get exciting prizes.
Attend the Accellera Tutorial
Title: Overview of UVM-SystemC