DVCon US 2020 | Agnisys

Are you looking at accelerating your SoC/IP development cycle by automatically generating the desired hardware-software interface (HSI) code for the different teams such as RTL designers, software/firmware engineers, verification engineers etc.? Are you concerned about the effort required to verify the HSI? Visit us at booth 801 in the DoubleTree hotel where we will show you how you can be confident about your verification.

When: March 04, 10:15am – 11:45Am

Where: FIR Room

The importance of Hardware-Software Interface (HSI) is growing as design teams struggle to create a golden register specification and test intent which can leveraged simultaneously by different teams such as software, RTL front-end, verification etc. across different platforms. As the number of registers in a SoC/IP increases exponentially, designers are realizing the need to specify the HSI at a higher level of abstraction and automatically generate the desired output code along with the corresponding verification suite. While there are several methods to creating a golden specification, SystemRDL, an Accellera standard has been steadily gaining traction and is now being adopted by a number of companies.

Attendees to this workshop will have a hands-on approach to creating a register interface using SystemRDL and then creating standard and custom sequences to verify it. Attendees will also learn how to leverage these custom implementation sequences to create high level test scenarios in PSS to ensure the same sequences are being used by the different teams across the different platforms, thereby accelerating the verification cycle.

Benefits to attending this workshop will include gaining a quick tutorial on SystemRDL including version 2.0 and its benefits, followed by creating custom implementation sequences. They will learn the benefits of using these custom sequences as building blocks for the high level test scenarios defined in PSS. Using the methodology outlined in the workshop, attendees will also learn how to organize and generate their correct-by-construction code for their designs from a golden specification and build a comprehensive verification environment to significantly reduce the development cycle.

In the complex SoCs and IPs of today, multiple clock domains and clock domain crossings are an accepted norm. There are several EDA tools which are available to identify the CDC issues in the RTL. But as the industry moves towards defining the design at higher levels of abstraction, using different bus protocols and multiple clock domains working at different frequencies, it becomes necessary to ensure non-existence of CDC related issues such as setup and hold time differences which further leads to a metastability state. In this paper we explore the definition of the Hardware-Software interface specification and then generating the RTL for different bus protocols showcasing the correct implementation of clock domain crossings with the help of handshake synchronizer.  The paper will also talk about the simulation results obtained for the implementation of a low power RTL design and techniques used for interconnection with various bus protocols.