SystemRDL to PSS BASIC TO PRO
Short workshop at DVCon US 2020:
For those who missed it can get the supporting docs here
Demos at DVCon – Schedule Meeting
- SoC Enterprise™: An Soc Generator and Assembler
- ARV-C™: SoC Virtual Prototype and Validation Environment Generation
- SLIP-G™: Standard Library of IP Generator
- Specta-AV™: UVM Testbench Generator for IP/SoC
- IDS-NG™: Show ML based sequence detection
When: March 04, 10:15am – 11:45Am
Where: FIR Room
Attendees to this workshop will have a hands-on approach to creating a register interface using SystemRDL and then creating standard and custom sequences to verify it. Attendees will also learn how to leverage these custom implementation sequences to create high level test scenarios in PSS to ensure the same sequences are being used by the different teams across the different platforms, thereby accelerating the verification cycle.
Benefits to attending this workshop will include gaining a quick tutorial on SystemRDL including version 2.0 and its benefits, followed by creating custom implementation sequences. They will learn the benefits of using these custom sequences as building blocks for the high level test scenarios defined in PSS. Using the methodology outlined in the workshop, attendees will also learn how to organize and generate their correct-by-construction code for their designs from a golden specification and build a comprehensive verification environment to significantly reduce the development cycle.
When: March 03, 10:30Am – 12:00 Pm
In the complex SoCs and IPs of today, multiple clock domains and clock domain crossings are an accepted norm. There are several EDA tools which are available to identify the CDC issues in the RTL. But as the industry moves towards defining the design at higher levels of abstraction, using different bus protocols and multiple clock domains working at different frequencies, it becomes necessary to ensure non-existence of CDC related issues such as setup and hold time differences which further leads to a metastability state. In this paper we explore the definition of the Hardware-Software interface specification and then generating the RTL for different bus protocols showcasing the correct implementation of clock domain crossings with the help of handshake synchronizer. The paper will also talk about the simulation results obtained for the implementation of a low power RTL design and techniques used for interconnection with various bus protocols.