Visit Agnisys at booth # 302.
- Monday, March 2: 5:00 - 7:00pm
- Tuesday, March 3: 2:30 - 6:00pm
- Wednesday, March 4: 2:30 - 6:00pm
Agnisys invites you to join at the Design Verification Conference and Exhibit (DVCon United States) at the Doubletree Hotel in San Jose from March 2-5, booth number 302. We are demonstrating new IDesignSpec innovations that enable automatic generation of design register and memory map code, UVM verification code with automatically annotated test plans, SystemC and documentation, all generated from a specification. Visit us to learn about our exciting solutions to speed up your chip design and verification process!
IDesignSpec™ is now the clear favorite tool for capturing hardware specifications for FPGA and Chip designs. We are offering a free evaluation of IDesignSpec with which you can create consistent, self-checking specifications that automatically generate high-quality code for RTL, Design Verification, Software and Documentation. Please use the link below to request an evaluation.
The December release of IDesignSpec expands support in virtually every area of the product based on customer feedback. Category enhancements include Signals, Clock Domain Crossing (CDC), Support for multiple BUS domains, Halt register handling, Counters, Expanded set of output formats (including SystemC, CMSIS-SVD, Perl, Python), Expanded file handling, RALF import, and of course our newest addition - Automatic Register Verification (see the description below).
Attendees who receive an Agnisys demonstration at DVCon get a chance to win a GoPro Hero digital camera!
One of the newest capabilities in IDesignSpec is Automatic Register Verification.
Automatic Register Verification (ARV) is a module that enables users to create the complete UVM based test bench and all the files required for complete UVM based verification of registers in a hardware device.
If you are not familiar with Automatic Register Verification, there is a video demo that walks through the complete methodology. The ARV Demo is the first video on the video demo channel.
Please sign up for a Free Evaluation of a SystemVerilog/UVM generator from Word, Excel, IP-XACT or SystemRDL.
If you cannot attend DVCon, then please feel free to watch one or more demonstration and webinar videos that show the full capabilities of IDesignSpec. Learn how CERN gained great benefits with IDesignSpec.
We look forward to seeing you at DVCon. If you cannot attend, please enjoy the demonstration videos and a free evaluation of IDesignSpec.