RISC-V SUMMIT 2019 – San Jose, CA

RISC-V is an open, free and extensible ISA enabling a new era of processor innovation through open standard collaboration. Using RISC-V companies can easily implement the minimal instruction set, well defined extensions and custom extensions to create custom processors for new and innovative workloads.

Visit our booth to see us demonstrate a flow using IDesignSpec, ISequenceSpec and ARV, which will showcase how hardware and software teams can accelerate their development of RISC-V based designs, targeted at both ASICs and FPGAs. With IDesignSpec, design teams are empowered to create a golden register specification, which can be leveraged by the software, hardware and verification teams to automatically generate the desired output – RTL, C-headers, UVM, pdf to name a few, – for different types of bus fabric such as AMBA® AXI/AHB/APB, TileLink, OCP, Avalon® and custom.

To accelerate IP verification and firmware development, design teams can also leverage ARV for standard and custom IPs to create standard sequences and generate the UVM environment and virtual prototyping models for a variety of platforms. With ISequenceSpec, we will show how design teams can create custom programming sequences to enable the software and firmware teams validate the hardware, thereby identifying potential hardware issues earlier in the product life cycle. By using tools from Agnisys, design teams can quickly automate their test environments for simulation, firmware development, emulation and post-silicon validation.

In addition, Agnisys also provides a rich standard library of completely customizable peripheral IPs such as PIC, I2C, Timer, GPIO, DMA, PWM etc., which designers can use to accelerate their development cycle.