
San Jose Convention Center,
150 W San Carlos St., San Jose,
CA – 95113
PRESS RELEASE:Agnisys to Demonstrate Solutions For RISC-V System Development at RISC-V Summit 2019
About RISC-V
What we will show
To accelerate IP verification and firmware development, design teams can also leverage ARV for standard and custom IPs to create standard sequences and generate the UVM environment and virtual prototyping models for a variety of platforms. With ISequenceSpec, we will show how design teams can create custom programming sequences to enable the software and firmware teams validate the hardware, thereby identifying potential hardware issues earlier in the product life cycle. By using tools from Agnisys, design teams can quickly automate their test environments for simulation, firmware development, emulation and post-silicon validation.
In addition, Agnisys also provides a rich standard library of completely customizable peripheral IPs such as PIC, I2C, Timer, GPIO, DMA, PWM etc., which designers can use to accelerate their development cycle.