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With the increasing complexity of IP/SoC designs, verification effort takes exceedingly more time. From creating a verification environment, test sequences, and configurations to plumbing every bit, a lot of manual steps are required. Because this process is manual, there is a high risk of bugs.IDS NextGen™ (IDS-NG) is a multi-platform product that helps users to write their own sequences with the help of ISequenceSpec™ (ISS) and generate automatic verification environments with the help of Specta-AV.Specta-AV is a superset of ARV and a comprehensive UVM testbench generator for IPs/SOCs. This tool automates verification using an industry-proven code generation technology. It can parse hierarchical register specifications from IP-XACT, SystemRDL, Word, or Excel, and retarget complex sequences into modelling languages such as SystemVerilog. Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for auto-generating UVM Tests/Environments/Agents. With the help of ISS, users can write/generate their own custom UVM sequences and the generated sequences can be integrated in the automatic UVM verification environment.

This webinar describes the steps to generate custom UVM sequences using ISS and how Specta-AV will include these and provide the best framework to generate complete UVM testbench including tests, sequence items, configurations, checkers, coverage, and all the connectivity automatically.

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Event Info:
Date : May 27th, 2021
Time : 10:00 AM-11:00 AM PDT

By May 27, 2021

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