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Various IP blocks within an SoC are often required to work in different asynchronous clock domains in order to satisfy the power constraints. Often, a metastability condition occurs which can lead to some consequences such as corrupted or lost data.

This webinar will revolve around the various techniques used to avoid metastability as signals cross from one clock domain to another and how these are handled in IDesignSpec..

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Event Info:
Date : June 18th, 2020
Time : 10:00 AM-11:00 AM PDT

Presenter: Abhishek Bora, Agnisys Senior R&D Engineer

By June 18, 2020

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