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With the increasing complexity in IP design, verification effort takes 70% of the total development time. From creating a verification environment, test sequences and configurations to plumbing all the bits and pieces, a lot of manual steps are required. And because it is manual, it is fraught with danger of bugs, tedious and not a good use of time.Specta-AV is a comprehensive UVM Testbench Generator for IPs/SOCs. This tool automates verification using an industry-proven code generation technology. With the ability to parse hierarchical register specification from IP-XACT, System RDL, Word or Excel, and the ability to retarget complex sequences into various modelling languages such as System Verilog, Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for autogenerating UVM Tests/Environments/Agents.

This webinar will show how Specta-AV provides the best framework to generate a complete UVM testbench including sequence items, configurations, checkers, coverage and even the plumbing within UVM automatically.

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Event Info:
Date : June 4th, 2020
Time : 10:00 AM-11:00 PM PDT

Presenter: Nikhil Arora, Agnisys R&D Engineer

By June 4, 2020

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