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IP verification is done at the block level focusing on its functionality. At the SoC level several types of bugs can

be identified, including inter-block connectivity, data routing, interrupt handling and overall functionality.

These require an SoC level verification environment

where the CPU is also part of the simulation and the stimulus is written in C. This webinar discusses the steps

to set up an SoC verification environment using RISC-V (SweRV design). The RISC-V tool chain will be introduced and used on a sample test case using compiler, assemble, linker for C and syncing with the SV_UVM counterpart.

Event Info:

Date : May 28th, 2020

Time : 10:00 AM-11:00 AM PDT

Presenter: Anmol Rana, Agnisys Senior R&D Engineer

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By May 28, 2020

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