WEBINAR: Register Design – Tips and Tricks in IDesignSpec | Agnisys

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RECORDED WEBINAR: Register Design – Tips and Tricks in IDesignSpec

Presented by: Nikita Gulliya, Agnisys R&D Engineer

IDesignSpec has become the de-facto solution for register design/verification. It has helped in the industry minimize SoC functional flaws that show up due to changes and errors in the functional specification by employing a golden specification methodology. IDesignSpec offers a wide-range of features and capabilities for various design use cases and strategies. As requested by many of our users, in this webinar, we will show you several design strategies and tips/tricks used by power-users of IDesignSpec.

This event has passed. To download slides and view recorded webinar, please fill the form below.

 

Agenda:

  • Tool Overview
  • Tips and Tricks
    • Building a Hierarchical Specification
    • Customizing the generated RTL
    • Widely-used RTL Properties
    • Parameterization
    • Connecting custom RTL to the auto-generated register block
    • Creating a TCL as a top-level check for limiting access types, register types, field widths
    • Feature-based availability at block, register and field level
  • Q & A

This webinar will be useful for:

    • Hardware Designers
    • Verification Engineers
    • Firmware Engineers
    • Emulation Engineers
    • System Developers
    • IP developers
    • SoC developers
    • Managers or Directors

 

By NO Comment September 19, 2019

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