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WEBINAR: Registers and Sequences: Design/Verification Best-Practices for Vertical ReusePresented by: Nikita Gulliya, Agnisys R&D EngineerThe register map is fundamental to today’s SoCs as it defines the configuration and control between CPUs and IPs. The register spec is inherently hierarchical and typically includes 3rd-party IPs (IP-XACT, SystemRDL or YAML formats) and custom IPs (Word or Excel formats). Register design and verification at the IP-level can be straightforward, but painful challenges start to creep up as the IPs are integrated into the subsystem and the final system. In this webinar, we discuss various verification use cases and sequences that are commonly used. We discuss the underlying challenges and demonstrate best-practices on how to reuse the auto-generated register RTL, UVM model, UVM test environment and configuration/test sequences at subsystem and final system.
Agenda:

  • Hierarchical Register Specification
  • Encompassing Sequence Specification
  • Design and Verification at various levels: IP, Subsystem and System
    • Use Cases and Tests
    • Challenges
    • Best-Practices to maximize reuse
  • Vertical vs Horizontal Reuse
  • Q & A

This event has passed. To download slides and view recorded webinar, please fill the form below.

This webinar will be useful for:

    • Hardware Designers
    • Verification Engineers
    • Firmware Engineers
    • Emulation Engineers
    • System Developers
    • IP developers
    • SoC developers
    • Managers or Directors

  

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