Webinar Series 2021 Details
Discover the Next Generation of IP/ASIC/FPGA/SoC Specification Automation. We will also discuss the latest innovations in our tools. Click on any registration button below to sign-up for one or more free webinars.
- IDS-NG for Automatic Verification Watch Recording
Date: 27-May-2021, Time: 10:00 AM-11:00 AM PDT
Description: With the increasing complexity of IP/SoC designs, verification effort takes exceedingly more time. From creating a verification environment, test sequences, and configurations to plumbing every bit, a lot of manual steps are required. Because this process is manual, there is a high risk of bugs.IDS NextGen™ (IDS-NG) is a multi-platform product that helps users to write their own sequences with the help of ISequenceSpec™ (ISS) and generate automatic verification environments with the help of Specta-AV.Specta-AV is a superset of ARV and a comprehensive UVM testbench generator for IPs/SOCs. This tool automates verification using an industry-proven code generation technology. It can parse hierarchical register specifications from IP-XACT, SystemRDL, Word, or Excel, and retarget complex sequences into modelling languages such as SystemVerilog. Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for auto-generating UVM Tests/Environments/Agents. With the help of ISS, users can write/generate their own custom UVM sequences and the generated sequences can be integrated in the automatic UVM verification environment.This webinar describes the steps to generate custom UVM sequences using ISS and how Specta-AV will include these and provide the best framework to generate complete UVM testbench including tests, sequence items, configurations, checkers, coverage, and all the connectivity automatically.
- IDS-NG for Design Watch Recording
Date: 10-June-2021, Time: 10:00 AM-11:00 AM PDT
Description: IDSNextGen™ (IDS-NG) is a multi-platform product that helps users create SoC specifications at the enterprise level. It handles individual IP to subsystem to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, and SystemRDL. IDS-NG generates design and verification code for both registers and sequences in one integrated environment. It helps to improve the productivity of FPGA/ASIC, IP/SoC, and System Development teams.
Agnisys products encompass an innovative register information management system to capture hardware functional specifications and addressable register specifications in a single “executable” specification. All downstream code and documentation for the addressable registers, sequences, interrupts, hierarchical aggregators, or SECDED can be generated from this single specification. This eliminates the inefficiencies around specifications in the digital design process and helps reduce the design cost, while improving quality and time to market.SLIP-G (Standard Library of IP Generators) from Agnisys offers configurable standard IP generators as an extension to addressable register generation. These IPs are designed to be easily customizable and configurable to meet any SoC requirements. IDS-NG automatically creates register specifications and generates RTL for standard IPs.SoC Enterprise (SoC-E) provides a flexible and customizable environment for SoC design assembly to comprehensively meet specific design requirements. It is not just an assembler as it can also generate RTL components such as bus aggregators, bus bridges (AHB-APB, AXI-APB, AXI4Full-AHBFull), muxes, and other “plumbing” components by leveraging the already existing and mature register solution.
- IDS-NG for Firmware
Date: 24-June-2021, Time: 10:00 AM-11:00 AM PDT
Description: Sequences are an ordered set of transactions on various interfaces or ports of a device. For example, a continuous set of steps that involve writing/reading specific bit fields of the registers in the IP/SoC which needs to be executed in an order. It can be used for programming for e.g. setting configurations, Reset, Power Up or can be used for testing the functionality. These sequences can be simple, or complex involving conditional expressions, array of registers, loops, waits on events, etc. These sequences are built on the registers/memories for an IP. IDSNextGen (IDS-NG) is a multi-platform product that helps users to create an IP and write portable sequences.How IDS-NG helps a firmware developer :
- Creates C based header files and tests automatically
- Ability to create custom programming sequences and test sequences.
- Standard APIs for Standard components that can be used to create larger sequences
With the help of IDS-NG custom user defined sequences can be generated. These sequences can be UVM sequences for verification, SystemVerilog sequences for validation, C code for firmware and device driver development, and various output formats for automatic test equipment (ATE).
This webinar goes through the overview of IDS-NG and how users can create custom sequences.
- IDS-NG for Documentation
Date: 08-July-2021, Time: 10:00 AM-11:00 AM PDT
Description: Documentation is an important resource to save project time and effort. It is also essential for quality and process control. Adopting one source that can be shared everywhere and manually describing details consumes a lot of effort.IDSNextGen™ (IDS-NG) automates this process by generating documentation in formats such as HTML, PDF, XML, CSV, and Word. These outputs contain all the information about the design specification.
- IDS-NG for System Verification
Date: 22-July-2021, Time: 10:00 AM-11:00 AM PDT
Description: This webinar covers how the Automatic SoC Verification and Validation (ASVV) tool focuses on system level validation and verification in an SoC development. It builds a systemlevel UVM and C based mixed environment based on the register layer generated using the single source captured golden register specification.ISS allows users to capture and generate custom test and functional sequences to check the intended behaviour of the design in the auto- generated verification environment.
- IDS-NG for Formal Verification
Date: 5-Aug-2021, Time: 10:00 AM-11:00 AM PDT
Description: IDSNextGen™ (IDS-NG) is a multi-platform product that helps users to write their own assertions with the help of ARV-Formal. ARV-Formal is a tool developed by Agnisys for verifying RTL designs without running simulation again and again after minor design changes. ARV-Formal uses a property checking technique that helps in different stages in ASIC/SoC project life cycle front end verification, logic synthesis, post-routing checks, and ECOs. Formal block-level verification, as a replacement for simulation for an IP, aims to prove the correctness of the system architecture for specific requirements such as cache coherence or avoiding deadlock conditions.
- IDS-NG for Safety-Critical Designs
Date: 19-Aug-2021, Time: 10:00 AM-11:00 AM PDT
Description: This webinar covers how functional safety is important for Agnisys tools and its application in these tools as well as in the tool development process. It also provides a preview into functional related documents from the user’s perspective.