Map Unavailable

Webinar Series 2021 Details

Discover the Next Generation of IP/ASIC/FPGA/SoC Specification Automation. We will also discuss the latest innovations in our tools. Click on any registration button below to sign-up for one or more free webinars.

  1. IDS-NG for Automatic Verification Watch Recording
    Date: 27-May-2021, Time: 10:00 AM-11:00 AM PDT
    Description: With the increasing complexity of IP/SoC designs, verification effort takes exceedingly more time. From creating a verification environment, test sequences, and configurations to plumbing every bit, a lot of manual steps are required. Because this process is manual, there is a high risk of bugs. IDS NextGen™ (IDS-NG) is a multi-platform product that helps users to write their own sequences with the help of ISequenceSpec™ (ISS) and generate automatic verification environments with the help of Specta-AV. Specta-AV is a superset of ARV and a comprehensive UVM testbench generator for IPs/SOCs. This tool automates verification using an industry-proven code generation technology. It can parse hierarchical register specifications from IP-XACT, SystemRDL, Word, or Excel, and retarget complex sequences into modelling languages such as SystemVerilog. Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for auto-generating UVM Tests/Environments/Agents. With the help of ISS, users can write/generate their own custom UVM sequences and the generated sequences can be integrated in the automatic UVM verification environment. This webinar describes the steps to generate custom UVM sequences using ISS and how Specta-AV will include these and provide the best framework to generate complete UVM testbench including tests, sequence items, configurations, checkers, coverage, and all the connectivity automatically.
  2. IDS-NG for Design Watch Recording
    Date: 10-June-2021, Time: 10:00 AM-11:00 AM PDT
    Description: IDSNextGen™ (IDS-NG) is a multi-platform product that helps users create SoC specifications at the enterprise level. It handles individual IP to subsystem to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, and SystemRDL. IDS-NG generates design and verification code for both registers and sequences in one integrated environment. It helps to improve the productivity of FPGA/ASIC, IP/SoC, and System Development teams.
    Agnisys products encompass an innovative register information management system to capture hardware functional specifications and addressable register specifications in a single “executable” specification. All downstream code and documentation for the addressable registers, sequences, interrupts, hierarchical aggregators, or SECDED can be generated from this single specification. This eliminates the inefficiencies around specifications in the digital design process and helps reduce the design cost, while improving quality and time to market. SLIP-G (Standard Library of IP Generators) from Agnisys offers configurable standard IP generators as an extension to addressable register generation. These IPs are designed to be easily customizable and configurable to meet any SoC requirements. IDS-NG automatically creates register specifications and generates RTL for standard IPs.SoC Enterprise (SoC-E) provides a flexible and customizable environment for SoC design assembly to comprehensively meet specific design requirements. It is not just an assembler as it can also generate RTL components such as bus aggregators, bus bridges (AHB-APB, AXI-APB, AXI4Full-AHBFull), muxes, and other “plumbing” components by leveraging the already existing and mature register solution.
  3. IDS-NG for Firmware Watch Recording
    Date: 24-June-2021, Time: 10:00 AM-11:00 AM PDT
    Description: A sequence is an ordered set of transactions on various interfaces/ports of a device. Often, a sequence is a continuous set of steps that involve writing/reading specific bit fields of the registers in the IP/SoC and need to be executed in order. Sequences can be used for setting configurations, resetting the device, powering it up, and testing its functionality. These sequences can be simple, or complex involving arrays of registers, loops, waits on events, parallelism, etc. IDS NextGen (IDS-NG) is a multi-platform product that helps users create an IP and write portable sequences for it:
    How does IDS-NG help a firmware developer?

    1. Creates C based header files and tests automatically
    2. Ability to create custom programming sequences and test sequences.
    3. Standard APIs for Standard components that can be used to create larger sequences

    With the help of IDS-NG, user-defined sequences can be created. Not only is the C Code generated from them, but also UVM sequences for verification, SystemVerilog sequences for validation, and various output formats for automatic test equipment (ATE).
    This webinar provides an overview of IDS-NG and shows how users can target firmware and software with it.

  4. IDS-NG for Documentation Watch Recording
    Date: 08-July-2021, Time: 10:00 AM-11:00 AM PDT
    Description: Chip/IP documentation is a critically important resource to save project time and effort. Keeping documentation in sync with the design is challenging. However, it is essential for better quality and process control. Adopting one source that everyone can work on and generate any format, for a variety of audiences is desirable. IDS NextGen (IDS-NG) helps teams to collaborate on the design specification and automatically generate documentation in formats such as HTML, PDF, XML, CSV, and Word. These outputs contain all the information about the design specification. The webinar will go over this critical but often underappreciated aspect of chip/IP development.
  5. IDS-NG for System Verification Watch Recording
    Date: 22-July-2021, Time: 10:00 AM-11:00 AM PDT
    Description: This webinar discusses verification and validation of SoCs in general and specifically with IDS-NG.
    A system level verification is an essential step to creating a flawless SoC.
    Join the webinar to see how to take IP level verification tests to the System Level. Get inside details about how to set up a UVM and C based mixed environment that will simulate a system level environment.
    See how to capture and generate custom test and functional sequences to check the intended behaviour of the design in an auto-generated verification environment
  6. IDS-NG for Formal Verification Watch Recording
    Date: 5-Aug-2021, Time: 10:00 AM-11:00 AM PDT
    Description:
    In this webinar we discuss the importance of auto-generating System Verilog Assertions. The SVAs are indispensable for formal verification, reducing the dependence on traditional simulation based verification. If any aspect of the chip specification can be captured formally then it can be transformed into SV Assertions. See how IDS-NG helps you create assertions from various forms of chip specification be it Register specification, Interrupt specification, Connectivity specification etc. This helps reduce the debug time and helps create correct-by-construction IPs/SoCs.
    We will also introduce an AI based Natural language to SVA generator.
  7. IDS-NG for Safety-Critical Designs Watch Recording
    Date:
    19-Aug-2021, Time: 10:00 AM-11:00 AM PDT
    Description:
    For Safety Critical designs the safety aspects need to be considered from the ground up. In this webinar we discuss how the IDS-NG FS tool helps teams to develop Functionally Safe designs. In addition to being a (soon to be) ISO26262 certified product, IDS-NG FS also helps users embed safety and fault tolerance aspects in the design right from the start.
By Comments off May 27, 2021