Webinar Series 2022 Details

Discover the Next Generation of IP/ASIC/FPGA/SoC Specification Automation. We will also discuss the latest innovations in SoC automation. Register below for free webinars.

1. Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™ Watch Recording
   Date: 28-Apr-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to formally verify your design by automatically generating SystemVerilog Assertions (SVA) for your block-level register specifications, chip-level RTL, and RTL connectivity at the SoC level using ARV-Formal™.
   
2. An Easy Solution for Automated Register Verification Watch Recording
   Date: 12-May-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to stress-test your registers in simulation by automatically generating your entire UVM testbench and supporting Makefiles for complete register verification using ARV-Sim™.
3. System-Level Validation with RISC-V Processors Watch Recording
   Date: 26-May-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to stimulate your RTL design with synchronized SoC testbench and RISC-V embedded tests using Automatic SoC Verification and Validation (ASVV™).
4. A Complete Automated UVM-Based Verification System Register Now
   Date: 9-June-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to automatically generate a complete UVM testbench for your addressable registers and application logic, including sequence items, configurations, checkers, coverage, and even the UVM plumbing, using Specta-AV™.
5. Automatic Creation of Pre-Validated RTL for Highly Configurable IPs Register Now
   Date: 23-June-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to automatically generate IPs designed to be easily customizable and configurable to meet your SoC requirements using the SLIP-G™ library of standard IP generators.
   
6. Centralized Creation of Portable Sequences from a Golden Specification Register Now
   Date: 7-July-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to describe the programming and test sequences of your device and automatically generate sequences ready to use from early design and verification stages to post-silicon validation using ISequenceSpec™ (ISS) .
   
7. From Cross-Platform Specification to Code Generation at the Enterprise Level Register Now
   Date: 21-July-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to capture your register and sequence specifications for IPs and SoCs from the individual IP to the enterprise level using IDS-NextGen™ .
   
8. A Smart and Automatic Assembly and Connections for SoCs Register Now
   Date: 4-Aug-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to automatically assemble and connect IPs from many different sources at SoC level using SoC Enterprise™. This includes automatic generation of components such as aggregators, bridges, channels, bus fabrics, muxes, etc. wherever needed.
   
9. Centralized Register Design and Verification from a Golden Specification Register Now
   Date: 11-Aug-2022, Time: 10:00 AM Pacific Time / 07:00 PM CET
   Description: Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your design and automatically generates all downstream views.