Welcome to the IDesignSpec Training Video Page

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IDesignSpec Video #1

Data Entry:

  • Simple Registers
  • Register Groups @ 3:05
  • Register Arrays @ 7:15
  • Memory @ 8:51
  • Creating Hierarchy @ 9:30
  • References @ 11:10

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IDesignSpec Video #2

Creating UVM Models:

  • Simple UVM Model
  • Adding Coverage @ 2:00
  • Adding HDL_Paths @ 4:08
  • Adding Constraints @ 6:21
  • Changing Default Classes @ 7:36
  • UVM Custom Code Insertion @ 8:18
  • UVM Properties @ 9:37

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IDesignSpec Video #3

Creating RTL Models:

  • Simple RTL Models
  • RTL Properties @ 2:02
  • External Registers @ 2:50
  • Adding Pipeline @ 3:22
  • Special Control Signals @3:53
  • Low Power Output @5:34

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IDesignSpec Video #4

Creating Complex Registers:

  • Interrupt Registers
  • Shadow Registers @ 7:53
  • Alias Registers @ 8:56
  • Indirect Registers @ 11:47
  • Trigger Buffer Registers @ 15:06
  • Lock Registers @ 16:20
  • UART Registers @ 17:44
  • Counters @ 18:53

IDesignSpec Video #5

Advanced Topics :

  • Multiple Bus Domains
  • Multiple Clocks @ 8:35
  • Clock Domains Crossing @ 11:05
  • Custom connections @ 17:02
  • Signals @ 22:11
  • Variants and RefVariants @ 38:34
  • Enum @ 46:6
  • Defines @ 50:31
  • Parameterization @ 53:59