Introduction

IDS-generated aggregation logic is used to control the slave, based on the input from the master, where it selects which block will operate. The generated aggregation logic is for a chip element which selects each child block based on the addresses and other factors from the master.

IDS generated RTL blocks have parameterized offsets with a default offset of ‘0’, which are overridden on their instance by the upper chip module for decoding of the actual registers with respect to the address map. And the generated aggregation logic selects and decodes these blocks on the basis of their absolute addresses.

IDS generated assignments to prdata, pready, and pslverr do not contain the muxing of active slave selection logic (i.e., block_name>_psel) and  generated aggregation logic has *pready as ANDed logic w.r.t the pready signal of the IDS generated blocks where it is assumed to be always ready to be accessed.

Figure-1: Basic block building in IDS

        Example of usage of 3rd party RTL:

IDS-NG Input

System RDL Input

   `ifndef IDS_UDP

         property aggregation_logic {type = string; component = addrmap; };

         property aggr_block_offset {type =string; component = addrmap; };              

     `endif

// chip : chip_top

addrmap chip_top {

  name = “chip_top Address Map”;

    aggregation_logic = “third_party”;

  addrmap elite_block1 {

    name  = “elite_block1 Address Map”;

    aggr_block_offset = “third_party”;

    reg reg_ram { 

       regwidth = 32;

      field {

        hw = rw;

        sw = rw; 

      } f1[31:0] = 32’h0;

    };

    reg_ram reg_ram @0x0;

  };

  addrmap ace_block2 {

    name  = “ace_block2 Address Map”;

    aggr_block_offset = “third_party”;

    reg reg_impact { 

       regwidth = 32;

      field {

        hw = rw;

        sw = rw;

      } f2[31:0] = 32’h0;

    }; 

    reg_impact reg_impact @0x0;

  };

  elite_block1  elite_block1 @0x0; 

  ace_block2  ace_block2 @0x4; 

    };    

In the above example, there is a top component “chip_top ” having two blocks/IPs, “elite_block1″ and “ace_block2″. The “elite_block1” and “ace_block2”  are third party RTL IPs/Blocks with the property “aggr_block_offset=third_party” applied. Whenever aggregation logic selects such a block , it will reduce its offset from the paddr before aggregating it to the block. The top component “chip_top ” has the property “aggregation_logic = third_party”, which will be used on the chip element to get an aggregator which contains the signals (prdata, pready, and pslverr)  assignment with the active slave selection logic.

 RTL output impact

. . .

assign prdata = ({32{elite_block1_ids_psel}} & elite_block1_ids_prdata) | ({32{ace_block2_ids_psel}} & ace_block2_ids_prdata);

assign pready = (elite_block1_ids_psel & elite_block1_ids_pready) | (ace_block2_ids_psel & ace_block2_ids_pready);

assign pslverr = invalid_address | (elite_block1_ids_psel & elite_block1_ids_pslverr) | (ace_block2_ids_psel & ace_block2_ids_pslverr);

. . .

        Conclusion:

IDS supports third party RTL integration with IDS aggregation logic. By using the above properties, IDS can modify the aggregation logic in the case of third party RTL integration.

Gurunam Singh

By NO Comment November 16, 2022

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