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Newsletter: Parameterization in IDS

Parameterization in IDS

In IDesignSpec parameters are constants that can be changed from the simulation command line. Typically, parameters are used for constants like number of clients, number of ports, inclusion/exclusion of blocks etc.

A parameter can have a value as a literal constant or another parameter or an arithmetic expression with constants and other parameters.

Parameters give us huge re-usability of the codes. It means we can use same module/code various times in a big design and each time it’s configuration can be different.

In IDesignSpec parameters can be passed to a module using three different methods: -

  1. Simple parameter passing
  2. Passing array via parameter.
  3. Bit slicing of parameters.

Property associated with SystemVerilog Parameter. Property “sv_param” for SV Header which converts the `define to the parameter inside the package.

1. Simple Parameter passing: -

In IDS, user is now able to specify parameters and defines in the define table typically at the top of the document and use these as macros to assign values to all properties.

Parameter Creation

  • Parameter’s name should start with ‘$’
  • Value of the parameter can be static or based on an expression. Both String and numeric expressions are allowed.

Rules for defining ‘parameters’

  • Parameter’s value can depend on already specified parameters.

Following example shows parameter and define creation in IDS-

IDSWord: -

In IDSWord, add a define template to parameters to the design spec.

 

p1
p2

p3
p4
p5

 

Verilog Code: -

module block_name_ids (

Reg1_enb,
Reg1_enb,
Reg1_Fld1_in,
. . .
. .
parameter Chip_off = ‘h1000 ; //
parameter Block_off = ‘h100 ; //
parameter Reg1_off = ‘h10 ; //
parameter Reg_group1_off = ‘h400 ; //
parameter Reg1_1_off = ‘h40 ; //
parameter Reg_def1 = ‘h70 ; //
parameter Reg_def2 = ‘h17 ; //
parameter Register_width = 16 ; //
parameter Num_lanes = 16 ; //
parameter NUM_CHANNELS = 80 ; //

parameter Reg_group1_count = Num_lanes;
parameter Reg_group1_address_width = 5;

parameter Reg1_count = NUM_CHANNELS % Register_width == 0 ?
NUM_CHANNELS/Register_width : NUM_CHANNELS/Register_width + 1;
parameter Reg1_address_width = 11;
. . .
. .

generate
genvar Reg1_i;
for( Reg1_i = 0; Reg1_i < Reg1_count; Reg1_i = Reg1_i + 1)
begin : Reg1_gen
. . .
. .

assign Reg1_offset[Reg1_i] = block_offset+(Reg1_off) * 1 + Reg1_i * ‘h4;
assign Reg1_decode[Reg1_i] = (address[Reg1_address_width-1 : 0] ===Reg1_offset[Reg1_i]) ? 1′b1 : 1′b0;

always @(posedge clk)
begin
if(!reset_l)
begin
Reg1_Fld1_q[Reg1_i] <= Reg_def1 + 4;
end
. . .
. .

if(!reset_l)
begin
Reg1_Fld2_q[Reg1_i] <= Reg_def2 *2;
end
. . .
. .

end //Reg1_gen
endgenerate

generate
genvar Reg_group1_i;
for( Reg_group1_i = 0;
Reg_group1_i < Reg_group1_count;
Reg_group1_i = Reg_group1_i + 1)
begin : Reg_group1_gen
. . .
. .
assign Reg_group1_Reg1_1_offset[Reg_group1_i] = block_offset+(Reg_group1_off) * 1 + Reg_group1_i * ‘h44 + (Reg1_1_off) * 1;
assign Reg_group1_Reg1_1_decode[Reg_group1_i] = (address[Reg_group1_address_width-1 : 0] ===Reg_group1_Reg1_1_offset[Reg_group1_i]) ? 1′b1 : 1′b0;
always @(posedge clk)
begin

if(!reset_l)
begin
Reg_group1_Reg1_1_Fld1_q[Reg_group1_i] <= Reg_def1 << 2;
end
. . .
. .
if(!reset_l)
begin
Reg_group1_Reg1_1_Fld2_q[Reg_group1_i] <= Reg_def2 >>1;
end
. . .
. .

   end //Reg_group1_gen
endgenerate
.          .         .
endmodule

2. Passing array via parameter: -

In IDesignSpec user can pass array using parameter for example:

The case below is passing unique parameters to repeated blocks. User can imagine the parameterized value something like an Interface ID.

We are instancing a block a parameterizable amount of times. The block has a register that is like an interface ID register, requiring unique values per instance.

Here, each block will use the default value, resulting in all interface ID’s having the same value.

We conclude that we could have the reset value of the interface ID register be controlled via a parameter, and when it is instanced in a repeat block, each repeat would get a unique value from the array (e.g. repeat index 0 gets parameter index 0, repeat index 1 gets parameter index 1 (if exists))

In the following example parameter is defined in 2-D format which is used in reg_name template later: The parameters are defined in the define table in the following manner:-

p6

Where $P1= name of the parameter [32] = is the width of the parameter [4] = is the depth of the parameter {0,1,2,3,4} = are the value of of the parameter

Below is the representation of how the parameters are used in a register:-

p7

Where the parameter name is given in the default value of the field and repeat property has been defined on the register with repeat value equal to the depth of the parameter.

Verilog Code: -

.          .           .
.          .
parameter Block1_ids_offset = ‘h14;
parameter reg [7:0] P1 [4:0] = ‘{1,2,3,4,6} ; //
parameter [3:0] p2 = 9 ; //
parameter addr_width = 6; parameter bus_width = 32;
.           .           .            .
.           .
generate

genvar section__i;
for( section__i = 0; section__i < section__count; section__i = section__i + 1)
begin : section__gen

.            .          .            .
.            .

always @(posedge clk)

begin
if (!reset_l)
begin
section__F1_q[section__i] <= P1[section__i];
end

.             .          .
.             .

3. Bit Slicing in Parameter: -

There is a way to specify the width of a parameter in IDesignSpec, and there is a way to create a parameter by bit-slicing an existing parameter in IDesignSpec.

like: -
$param1[24] = 0xABCDEF
$param2[8] = param1[23:16]
$param3[8] = param1[15:8]
$param4[8] = param1[7:0]

The parameters are defined in the define table in the following manner:-

p8

Where,

$param1, $param2, $param3, $param4= name of the parameter

[32]= is the width of the parameter
0xABCDEF = is the value of the first parameter
“$param1[23:16]” = where $param2 is assigned the [23:16] values of $param1

These values can later be used in the register fields by declaring them in the register field in the default value part:

p9

Here, the field is assigned the value of the parameter.

Verilog Code: -

.           .           .           .
.           .
parameter [31:0] param1 = ‘hABCDEF ; //
parameter [7:0] param2 = param1[23:16] ; //
parameter [7:0] param3 = param1[15:8] ; //
parameter [7:0] param4 = param1[7:0] ; //
.           .           .           .
.           .
always @(posedge clk)
begin
if (!reset_l)
begin

           Section1_f1_F1_q <= param2;
end

.           .           .           .
.           .

Property- sv_param: -

The property sv_param is applied on the top-level module for SV haeader outputs. It converts the `define to the parameter inside the package.

Below is the example for the same:

p10

SV Header Output: -

package block_name_header_pkg; parameter BLOCK_NAME_ADDR = ‘h00;
parameter BLOCK_NAME_SIZE = ‘h90;
parameter BLOCK_NAME_MEMORY_NAME_ADDR = ‘h00;
parameter BLOCK_NAME_MEMORY_NAME_SIZE = ‘h4;
parameter BLOCK_NAME_MEMORY_NAME_DEPTH = 32;
parameter BLOCK_NAME_MEMORY_NAME_MASK = ‘hFFFFFFFF;
parameter BLOCK_NAME_REG_GROUP_NAME_ADDR = ‘h80;
parameter BLOCK_NAME_REG_GROUP_NAME_SIZE = ‘h8;
parameter BLOCK_NAME_REG_GROUP_NAME_REPEAT = 2;
parameter BLOCK_NAME_REG_GROUP_NAME_REG_NAME_ADDR = ‘h80;
parameter BLOCK_NAME_REG_GROUP_NAME_REG_NAME_DEFAULT = ‘h00000000;
parameter BLOCK_NAME_REG_GROUP_NAME_REG_NAME_F1_MSB = 31;
parameter BLOCK_NAME_REG_GROUP_NAME_REG_NAME_F1_LSB = 0;
.             .              .             .
.             .              .
typedef struct packed {
logic [31:0][31:0] memory_name; block_name_reg_group_name[2] reg_group_name;
}  block_name;

endpackage

Summary:

This article has shown how parameters are handled in IDesignSpec. Parameter arrays have also been supported. These make a very generic specification for IP/SoC. It goes to show the versatility of IDesignSpec.

By: Anmol