+1 855-VERIFYY
+

Newsletter: Serial Peripheral Interface

Spotlight Is ON

Resources:

Evaluate a full version of IDesignSpec - System Verilog Code Generation for UVM Verification

IdesignSpec Datasheet for Register verification

Download DVinsight a SV UVM IDE

DVInsight Data Sheet

SPI:(Serial Peripheral Interface)

The Serial Peripheral Interface bus (SPI) is a synchronous serial communication interface specification used for short distance communication. The SPI bus specifies four logic signals:

  • SCLK: Serial Clock (output from master).
  • MOSI: Master Output Slave Input, or Master Out Slave In (data output from master).
  • MISO: Master Input Slave Output, or Master In Slave Out (data output from slave).
  • SS: Slave Select (often active low, output from master).

spi1

SPI with IDS internal signal connections

SPI in IDS

In order to synchronize SPI bus with IDS proprietary bus we will be taking this information from the master through the data line (MOSI). So, for a read or write cycle, first 8 bits will be the IDS instruction set, next 8 bits will be the address of the register to which it wants to communicate and next will be the data bits which depend on the bus width of the proprietary bus.

Regarding the IDS Instruction Set: -

spi2

read/write.

For 8-bit instruction set, the maximum value of bus width of proprietary bus will 32 bits.

Implementation

There will be a SPI slave widget which will convert the serial data received from master/user into parallel data or parallel data from IDS RTL into serial, then this data will be received or given to proprietary bus which then communicate with the IDS rtl.

There will be no new property, we just have to instantiate this widget into IDS rtl.

Customer can use this widget just like they are using our other widgets.

Note :- SPI supports only CPOL=0 ,CPHA=0 transfer mode.

Timing Diagrams

Below is an example of a read/write transaction for a 8 bit register having address (8’b00000000).

Write Transaction:-

spi3

Read Transaction:-

spi4

Summary :

The SPI bus is a synchronous serial communication interface specification used for short distance communication. In order to synchronize SPI bus with IDS proprietary bus, information will be taken from the master/user through the data line (MOSI). So, for a read or write cycle, first 8 bits will be the IDS instruction set, next 8 bits will be the address of the register to which it wants to communicate and next will be the data bits which depend on the bus width of the proprietary bus.

By: Anmol