We are happy to bring to you the 2nd issue of the Agnisys newsletter on schedule. This newsletter comes directly from the Engineering team that is constantly working on improving the products. You will find much more in-depth content that show the power of our products : IDesignSpec and DVinsight. We cover IP-XACT, Datasheet generation, advanced timers and counters in IDeisgnSpec and finally the cool features of DVinsight. As always your comments and suggestions are welcome.
– Anupam Bakshi, CEO, Agnisys, Inc.
Agnisys has been in a relentless pursuit of system development with certainty. Uncertainty in the development process leads to a lot of time waste and productivity loss. To fix this, one has to move the specification from a classical document into one that is machine readable. In addition, one can use tools that ensure that you cannot make mistakes – be it using smart editors that are content aware or using well established flows. The idea always is to reduce or even eliminate debug time and time for verification itself.
Simplify IP-XACT flow for IP/SoC development
IP-XACT from the IEEE 1685-2009/2014 is nowadays recognized by the electronics community as the most appropriate choice for properly and efficiently managing Electronic System Level (ESL) flows. IP-XACT describes an EXtensible Markup Language (XML) data format and structure, documented with schema for capturing the meta-data, which documents design intellectual property (IP) used in the development, implementation, and verification of electronic systems. Read more
Automatic Datasheet Generation with IDesignSpec
One of the real advantages of IDesignSpec is its ability to create Word output files from register specifications. This allows you to automatically document the register specification for everyone on your project. The format of the output files can be specified via user defined templates. IDesignSpec understands special keywords that are substituted for real data when generating the files.
The interesting thing about this flow is that the input can be any of the formats that IDesignSpec takes in, such as, IP-XACT, SystemRDL, CSV, Excel or even Word. The output can be a Word datasheet or a PDF version of it. Looking at an IP-XACT, SystemRDL or even CSV or Excel is not the same as a Word or PDF datasheet. While these formats may be good for machines, they are not always appropriate for human consumption. Read more
Generating Counters, Interrupts, Timers using IDesignSpec
System on a chip (SoC) consists of several different microprocessor subsystems together with memories and I/O interfaces. Counters, Interrupts and Timers are a basic building-block of every electronic system. Counter and timer hardware is a crucial component of most embedded systems. A microcontroller may be in-built with one or more timer or counters – to control all counting & timing operations within a microcontroller, count external pulses and also interrupts the processor on a certain count value. Hence, timers/counters and interrupts are widely used concepts in systems.
IDesignSpec consists of many features to include different types of timers, counters and interrupt logic in the design specification. Hence, using IDesignSpec’s counter and interrupt features/properties one can very easily specify counter, interrupt and timer specifications to be used in the design and automatically generate the code for it. Read more
Eliminating “muda” in creating UVM based environments with DVinsight.
Since the advent of UVM for design verification, gone are the days of single file environment for verification. These days’ design/verification (DV) engineers have to spend a lot of time managing lots of code in hundreds of files. Understanding the class relationship, the inheritance hierarchy, and the types of various handles, etc. makes the DV engineers less productive.
There was a need of a “smart” editor which would enable DV engineers to write correct-by-construction code and eliminate “muda” from the DV process.
We created DVinsight by bringing together the best that modern technology has to offer. It has been purposefully crafted to be a companion for every DV engineer. It helps engineers to produce the code without coming in the way. Read more