Agnisys tools have an amazing set of enhancements. The major new enhancements include Formal Verification through ARV-Formal™, support of chip-inside-chip with input IDS-Word, IDS-Excel, IDS-NG, SystemRDL, and, IDS-Calc, Support of Tight Generator Interface in SoC-E, and Tool Qualification Kit for Functional Safety Compliance.
ARV-Formal™ is a tool developed by Agnisys Inc. for verifying RTLs without running simulation again and again after any minor changes in the RTL. There are different formal techniques such as “Formal Equivalence Checking” and “Formal Property Checking”. Read More
Now a chip can be a container for other chip hierarchies in addition to block hierarchies. For removing the limitation on the number of hierarchies over block level, chip-inside-chip is now supported with input IDS-Word, IDS-Excel, IDS-NG, SystemRDL, and IDS-Calc. Read More
SoC-E is now enhanced with the support of TGI API for IPs described in IP-XACT XML documents. In SoC-E using these APIs users can access, modify, delete and create design data according to their own requirements. Read More
Agnisys provides the Tool Qualification Kit (TQK) as an exclusive pre-qualification kit for its IDesignSpec™ tool suite to users embarking on a functionality safe design and not worrying about adding any additional measures for safety compliance in their design development processes involving this EDA tool suite. Read More
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