In our first Newsletter of 2022 we are drawing your attention to new capabilities in the IDesignSpec family of products. We hope that this will give you an overview and our release notes and documentation will enable you to go deeper and make the most of the products you have at your disposal.
Various new enhancements have been introduced recently in products such as IDesignSpec™ (IDS), IDS NextGen™ (IDS-NG), SLIP-G™, and ISequenceSpec™ (ISS). Significant new enhancements in IDS include a new capability using SVG output to represent the specification in a more elegant graphical representation in two dimensional file format. This output is very useful in case of large specifications. Also, a new property has been supported to control multibit inference for all bused registers. It is a technique for HDL designers to map the signals in RTL design for low power.
ISS also has been enhanced with a read_check feature which is required in a test to check whether a value that has been written to a register is the same as the value that has been previously written. With this feature, it becomes handy to get overall errors about the test sequence.
New IP, Universal Asynchronous Receiver Transmitter (UART) , has been added to the library of standard IPs. This block provides the controller with the functionality of asynchronous serial data transfer.
A new tool IDS-FPGA has been unveiled which is an integrated solution uniquely poised to specifically target FPGA designs to speed up the development while maintaining quality, based on Agnisys’ decade-long experience in specification driven development. This will solve the need of the FPGA designers by providing them an easy-to-use system to design, verify and target the FPGAs.
As always, your comments and suggestions are welcome.
UART in SLIP-G : SLIP-G™ (Standard Library of IP Generators) from Agnisys offers configurable standard IP generators as an extension to its addressable register generator tool. These IPs are designed to be easily customizable and configurable to meet any SoC requirement. IDS automatically creates register specifications and generates RTL for standard IPs. A new IP, UART, is added in the standard library. Read More
Synthesis directives : A multibit component (MBC), such as a 16-bit register, reduces the area and power in a design. But the primary benefits of MBCs are the creation of a more uniform structure for layout during place and route and the expansion of the synthesized area of a design. Read More
SVGalt2 Output : IDS has introduced a new capability using SVG output to represent the specification in a more elegant graphical representation in two dimensional file format. Read More
Read_Check feature in ISS : Oftentimes, in the verification/validation environment, it is required in a test to check whether a value that has been written to a register is the same as the value that has been previously written. If the values are mismatched then an error should be flagged. Read More
IDS FPGA : IDS-FPGA is an integrated solution which is uniquely poised to specifically target FPGA designs to speed up the development while maintaining quality, based on Agnisys’ decade-long experience in specification driven development. This will solve the need of the FPGA designers by providing them an easy-to-use system to design, verify and target the FPGAs. Read More
