Accuracy of Register Verification
Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation. That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface.
A Verification Engineer has to develop a coverage driven models manually to verify a design. So s/he has to spend a large amount of time in verifying the functionality of a register and memory map of the design. This issue is futher exasserbated when there are a large number of IP with registers in an SoC design.
ARV is an application that provides the complete solution for implementing a register verification methodology. The Automatic Register Verification (ARV) module works with IDS. ARV automatically generates the entire test bench, verification plan and Makefiles for complete register verification.
So most of the register verification related problems can be resolved by using ARV.
Rewards of ARV
- ARV Ensures that the Register Implementation, which is either generated automatically or manually created, meets the specification.
- UVM does provide standard register and memory tests like : uvm_reg_hw_reset_seq, uvm_reg_bit_bash_seq ,uvm_reg_access_seq etc. However, these have limitations and give only about 60% functional coverage out of the box. User has to manually put in effort to cover the remaining 40%.
- ARV ensures that the coverage metrics are achieved from all three simulators. ARV also provides make file for all three simulators (Questa/VCS/IRUN). So by using makefile , user can very quickly generate functional coverage as well as code coverage report for every simulator.
- ARV supports testing for special registers like, lock registers, shadow registers, register aliases, interrupts, volatile, sync FIFO etc. It generates sequences for these special registers.
- ARV verifies Memories, Unregistered field and External Hardware component.
- ARV ensures that the application logic correctly interfaces with the registers and memories.
- ARV creates negative tests to verify holes in the memory map.
- ARV generates special tests to cover unexpected behaviors from registers.
- Automatically creates register-focused coverage reports.
- ARV provide a ready-made push-button genertin of an entire UVM environment. This can be used as-in or additional sequences for reading and writing can also be added in the environment.
- ARV can import IP-XACT, SystemRDL, RALF, Word, Excel, CSV, XML and host of other formats.
- ARV supports all software access modes for all fields and also the registers with side effects. Examples like – W0t(Write Zero to toggle) , rc (read to clear), Ws(write to set), w0crs(write zero to clear and read to set) and many more access are supported in ARV.
- Special tests for Multiple bus domains, async FIFOs and shared registers are also supported*.
Imagine doing all this verification by hand without ARV.
As mentioed above ARV provides high quality complete register based coverage driven verification environment . ARV automatically generates entire test bench, verification plan ,Makefiles for all three simulator(Questa/VCS/IRUN) so that user can verify design without giving more manual efforts.