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Newsletter:Bigger regwidth registers in IDesignSpec

Bigger regwidth registers in IDesignSpec

IDesignSpec is an EDA tool that solves most of the designer’s problems, in minutes rather than hours. In every release we work to make some improvements and enhancements to make our tool the World’s best. In this release, we did something that was asked by our customers to support registers having width greater than the selected bus width. Although, supporting this particular feature required a lot of research and was a brainstorming exercise for our engineering team.

For quite a sometime, we had been putting off the implementation of register width greater than bus width as were searching for the best algorithm to support bigger regwidth registers that can take lesser time while reading and writing from the bus– for all combinations of registers, fields and busses.

When an IP is reused, the bus access width can change based on the bus it is connected to. Having reusable IPs allow SoC architects to explore various ways to connect them. The need for this feature arises when you want to create a register spec independent of the bus access width.

In different flavours of IDesignSpec i.e. IDS Word, IDS Excel and IDS Cal, bus width can be selected in Configure->Bus Width. While in IDS Batch, there is option “-bus_width <8|16|32|64>”. In addition to this, we also confirm that the regwidth of registers should be a multiple of the bus width.

Depending on the bus width, there would be n (regwidth divided by bus_width) wr_valids, rd_valids and offsets. Based on the value of n wr_valids, write occurs on the buffer signal for each of the field and same as that for the rd_valids, which is responsible for reading data.

Moreover, while supporting bigger regwidth registers, we made sure that there should not be any delay, as there might be a case when a field crossing its boundary, in that scenario there would be a write depending on the previous decode and present decode signal.

Here is an example:



This example will show how a register of 32 bit read and write data with bus_width of 8 bit. There are 4 wr_valids, rd_valids and offsets. These four offsets will turn on or off to four different decodes, and these decode when combines with rd_stb and wr_stb activate rd_valids and wr_valids respectively.

assign Reg1_wr_valid0 = Reg1_decode0 && wr_stb;

assign Reg1_wr_valid1 = Reg1_decode1 && wr_stb;
assign Reg1_wr_valid2 = Reg1_decode2 && wr_stb;
assign Reg1_wr_valid3 = Reg1_decode3 && wr_stb;
assign Reg1_rd_valid0 = Reg1_decode0 && rd_stb;
assign Reg1_rd_valid1 = Reg1_decode1 && rd_stb;
assign Reg1_rd_valid2 = Reg1_decode2 && rd_stb;
assign Reg1_rd_valid3 = Reg1_decode3 && rd_stb;
assign Reg1_enb = Reg1_wr_valid0;
assign Reg1_offset0 = block_offset+‘h0;
assign Reg1_offset1 = block_offset+‘h0 + ‘h1 ;
assign Reg1_offset2 = block_offset+‘h0 + ‘h2 ;
assign Reg1_offset3 = block_offset+‘h0 + ‘h3 ;
assign Reg1_decode0 = (address[block_name_address_width-1 : 0] == Reg1_offset0[block_name_address_width-1 : 0] ) ? 1′b1 : 1′b0;
assign Reg1_decode1 = (address[block_name_address_width-1 : 0] == Reg1_offset1[block_name_address_width-1 : 0] ) ? 1′b1 : 1′b0;
assign Reg1_decode2 = (address[block_name_address_width-1 : 0] == Reg1_offset2[block_name_address_width-1 : 0] ) ? 1′b1 : 1′b0;
assign Reg1_decode3 = (address[block_name_address_width-1 : 0] == Reg1_offset3[block_name_address_width-1 : 0] ) ? 1′b1 : 1′b0;


Similarly, while a field is writing through bus, same always block is used to write a complete field in two cycles when the field is crossing the bus boundary.

    if (Reg1_wr_valid0) // FIELD : SW Write
Reg1_Field_q[7 : 0] <= ( wr_data[7 : 0] & reg_enb[7 : 0] ) | (Reg1_Field_q[7 : 0] & (~reg_enb[7 : 0]));

    if (Reg1_wr_valid1) // FIELD : SW Write
                  Reg1_Field_q[15 : 8] <= ( wr_data[7 : 0] & reg_enb[7 : 0] ) | (Reg1_Field_q[15 : 8] & (~reg_enb[7 : 0]));


Finally, when a read occurs, there is a read back mux to read the bits from the field making 4 rd_data and then OR-ing those rd_datas in rd_data that is a bus signal.


assign Reg1_rd_data0 = Reg1_rd_valid0 ? {Reg1_Field_q[7 : 0]} : 8′b00000000;
assign Reg1_rd_data1 = Reg1_rd_valid1 ? {Reg1_Field_q[15 : 8]} : 8′b00000000;
assign Reg1_rd_data2 = Reg1_rd_valid2 ? {Reg1_Field2_q[7 : 0]} : 8′b00000000;
assign Reg1_rd_data3 = Reg1_rd_valid3 ? {Reg1_Field2_q[15 : 8]} : 8′b00000000;
assign Reg1_rd_data = Reg1_rd_data0 | Reg1_rd_data1 | Reg1_rd_data2 | Reg1_rd_data3;


We have supported almost all properties that work when the regwidth is equal to bus_width.

In Summary, we would like to share that now from IDesignSpec release version bigger regwidth registers i.e. registers having width greater than the bus_width, are now supported in Verilog and soon it will be supported in VHDL, UVM and ARV too. Different properties that are supported earlier are supported with this new enhancements with just a few limitations. We always try to make our tools better with the help of our customers. We hope user will use this feature and provide us valuable feedback – that’s what keeps us going!


By: Nikhil