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Newsletter:HDL PATH for Gate Level Simulation

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HDL PATH for Gate Level Simulation

IIn UVM, the register abstraction layer describes the register and memory behavior of the Design Under Test (DUT). An “hdl_path” is specified for the RTL storage of the registers. When the Gate level simulation is performed, the corresponding hdl_path properties need to be added.

We can read/write the register or memory with two methods:

  1. Front door access: It completes read/write operation by bus and consumes clock cycles.

  2. Back door access: It completes read/write operation by back door access i.e. simulator database and operation completes in zero time. This method uses ‘hdl_path’ property.

IDS supports the use of front and back door access methods to read/write the register or memory data.

The property ‘hdl_path_gates’ is supported at chip, block, reggroup, register, and field level in the same way as the property ‘hdl_path’. Both properties can be simultaneously added to the model. The value of hdl_path_gates can be an explicit string, or a string pattern.

It has zero time simulation for read and write through peek() and poke() respectively. Therefore, it increases the efficiency.

When the synthesis of RTL is performed, the gate level netlist is completely different with different storage elements and different instance names. Fortunately, these instance names created by the synthesis tool have some order (usually) so that we can provide a pattern to the hdl_path_gate property which will refer to the equivalent storage in the RTL.

  1. How to add multiple hdl_path_gates?

hdl_path_gates=”ff1.q, ff2.q”

If a field is split into multiple gate level storage elements, one can specify a list of elements.

  1. Automatic generation of hdl_path_gates from hdl_path using patterns

Hdl_path = reg1_FF_q

Hdl_path_gates= %r_%f_q

Where %r and %f are the name of the register and field respectively.

hdl1
hdl2
hdl3

The above can be specified in a more generic way by using patterns for block (%b), register (%r) and field (%f) as shown below.

hdl4hdl5hdl6

Here %M= value of field MSB,   %L= value of field LSB
%c =Chip name,       %b=Block name,      %s=Reg Group name ,
%r=Register name, %f=Field name, %m=Memory name
All small letter operator can add comma separated value before (prefix) and after(Suffix) .
As: \ %r . will generate as \Reg1.

Generated UVM code:

add_hdl_path(“Block1″,”GATES”);

Reg1.clear_hdl_path();
Reg1.add_hdl_path_slice(“Reg1.Fld1_q_.regout”, 31, 1, ,”GATES”);
Reg2.clear_hdl_path();
Reg2.add_hdl_path_slice(“Reg2mode_q_31_.regout”, 31, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode1_q_20_.regout”, 20, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode1_q_19_.regout”, 19, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode1_q_18_.regout”, 18, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode1_q_15_.regout”, 15, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode1_q_12_.regout”, 12, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode1_q_11_.regout”, 11, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode2_q_10_.regout”, 10, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode2_q_9_.regout”, 9, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode2_q_8_.regout”, 8, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode2_q_7_.regout”, 7, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode2_q_6_.regout”, 6, 1, ,”GATES”);
Reg2.add_hdl_path_slice(“Reg2Mode2_q_5_.regout”, 5, 1, ,”GATES”);

Mem1.clear_hdl_path();
Mem1.add_hdl_path_slice(“Mem1″, 0, 32, , “GATES”);

Usage Models

set_hdl_path_root( ,“GATES”) ;
set_hdl_path_root( ,“RTL”);

Testing process:-

We are using ARV environment for testing.
The top level hdl path can also be defined in the uvm environment class in the arv directory

“ids output directory -> arv -> env -> env.svh” as:

begin

string hdl_root=” wrapper.u_dig_top.u_controller_bist_top.u_controller_top.u_ids_top.u_reg_map”;
void’($value$plusargs(“ROOT_HDL_PATH=%s”,hdl_root));
cfg.model.set_hdl_path_root(hdl_root, “GATES”);
cfg.model.set_hdsssl_path_root(hdl_root, “RTL”);
void’(cfg.model.set_coverage(UVM_CVR_ALL));

end

 

The testing sequence file “ids output directory -> arv -> sequences -> arv_seq_lib.sv” contains library of register sequences to test the DUT. The design abstraction models (“RTL” or “GATES”) is specified in the register peek/poke methods used for backdoor access.

Examples:

rg.poke(status, write_val .parent(this),.kind(“GATES”));
rg.peek(status, read_val, .parent(this),.kind(“GATES”));

Notes:
The functionality is same as the property hdl_path, only enhanced.

 

By: Tarun