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Newsletter:I2C Supported in IDS

I2C Supported in IDS

IDS now supports the Serial interface via the I2C bus protocol. Various operating modes are implemented.

It contains the I2C-bus data transfer, handshaking and bus arbitration schemes. I2C widget is implemented for 7 bit addressing mode as user will specify the address of the device as slave address. Which will be user specified. 8-bit register address is supported for read and write the data. The I2C widget will take data into I2C format from I2c Master device and converts it to proprietary interface.

I2C0

i2c with IDS internal signal connections

 

User can easily communicate with IDS serially using I2C master from the host (software) side. There are some initial configurations before starting with I2C: IDS provides a way to configure these initials at the beginning itself. It provides the user with configurable bus select option, I2C then selects device addressing mode and slave address.

The I2C provides an interface between the Master and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.

Most TI devices (c5000, c6000, OMAP, Davinci, etc.) use the underlying modules.

Supported Bus Features

  • Compatible with Philips I2C Standard. Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
  • Single master operation
  • Software programmable clock frequency, Generally 3 Transmission speeds: Normal, Fast, and High Speed.
  • Clock stretching and wait states generation.
  • Software programmable acknowledge bit.
  • Interrupt or bit polling driven for each byte.
  • Start, Stop, Repeated Start detection.
  • Supports 7 bit with configurable address masking in slave mode.
  • Supports strict I2C reserved rule, Detects general call addresses.
  • Support for IDS compatible byte format transfer for Register address.
  • Bus busy detection.

 

i2c with IDS internal signal connections

The I2C Widget provides an interface between I2C Slave (A Two wire information) and IDS internal signals. This widget can be used at software side of the IDS and provides a way of introducing serial communication channel for the clients.

FSM Diagram for I2C Widget

I2C1

A finite state machine for I2C controller

 

7-bit Slave Address and RD/WR bit Format

After the START condition (S), a slave address is sent. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W) — a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request for data (READ).

A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.

 

I2C2

A complete Data Transmission by I2C

 

Configurable Addressing

IDS provide a facility to configure 7-bit addressing of a particular device before start generation of I2C Interface with IDS. This addressing follow all the rules and regulations complaint with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1.

8-bit of Register Address:

After the slave address is acknowledged, user needs to send a byte that is a specified IDS register address which is byte addressable by the increment of four bytes for each register.

If there is a memory specified, this controller will take care of an appropriate address calculation or an offset value compatible with IDS requirements.

Because the default address of an IDS registers is 32 bit, widget will split this address into separate bytes which are followed by one after the other covering the full register by using repeated Start logic.

Summary

In addition to I2C we have also supported the SPI bus. Please contact support for access to these widgets and latest executable with the new support.

 

By: Harshit