Indirect Registers inside Reggroups
In memory mapped digital designs, when you have a limited address space, but you have a need to access a larger memory you use indirect address space. Indirect address space is typically implemented using an index register, a data register and an indirectly addressed memory. IDesignSpec fully supports this scheme in both RTL and UVM.
Recently, we came across a situation where our customers were using the indirect registers inside the reggroups, in addition, the bus width for the direct and the indirect bus was different. This required some specially handling in UVM and RTL. We supported indirect register inside the reggroups with different bus widths.
Using IDesignSpec we can create indirect access of a memory thru two registers – an “index” register and a “data” register. This index-data association is created by adding a property on the data register called “index_reg” and giving it value as name of the Index register.
This one property creates the indirect register access and IDesignSpec automatically creates the RTL, UVM and ARV.
In certain applications the bus communicates directly with a bank of 8 bit registers. There may be another block of wider registers say 32-bit which is accessed indirectly through the 8-bit registers. This can be represented in IDS by the following example -
Here the 8-bit registers (Data0, Data1, Data2, Data3) are grouped together by specifying the property “datagroup = A” on each of them. Where the value “A” is the group name.
The property “indirect_map=Indirect_regmap” is used to specify the indirect registers arrays(32-bit in the indirect map), which is accessed by the index and (Data3 to Data0) data registers in the direct map.
In the UVM Reg Model, the reg_goup is a class extended from uvm_reg_file. Along with index register and data registers, it contains the instantiation of larger memory to be accessed. The Data3 register which is trigger register is configured with the use of index register and larger memory array.
Implicitly a write/read on Data3 triggers write/read to the indirect registers in the indirect_map. You could also explicitly specify properties to trigger read/write to indirect registers by following properties:-
hw_rd_trigger = index, wr
Where a write to the “index” register(8bit) triggers read from the indirect registers (32bit)
Where a write to the “Data3” register(8bit) triggers write to the indirect registers (32bit)
The property “datagroup.order= Data0, Data1, Data2, Data3” specifies the order, where Data0 is MSB.
This whole functionality of indirect registers can be tested with the use UVM regModel and Automatic Register Verification(ARV). ARV has special sequences for testing the indirect registers with the corner cases.
We have shown how easy it is to create indirect registers, inside or ourside reggroups, with same or different buswidths in IDesignSpec. Using these simple properties make the specification very powerful to describe any user scenario. The benefit of automatic RTL, UVM and sequences as a result of these properties is a huge value add and a time saver.