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Newsletter:IP-XACT Design Hierarchy

IP-XACT Design Hierarchy

IP-XACT is an industry standard IEEE 1685-2009/2014 which is recognized by the electronics community as the most appropriate choice for properly and efficiently managing Electronic System Level (ESL) flows. With more complex System Level Designs and IP Components, it is difficult for design and verification engineers to build, integrate, update and verify the design hierarchy. The IEEE 1685 IP-XACT standard was designed to fit this requirement. It not only supports the creation of IP and Design level documents but also provides a mechanism for their interconnection.


What is IPXACT?

IP-XACT describes an EXtensible Markup Language (XML) data format and structure, governed by a schema for capturing the meta-data, which captures the design of intellectual property (IP) used in the development, implementation, and verification of electronic systems.

IP-XACT schema defines a number of document types, and a set of semantic rules that describe the relationships between those documents.

Here are the main document types in IP-XACT:

  • Component documents

Component document has several XML tags and attribute that contains IP specific architectural and interconnection information.
Some of those XMLtags are:

  • memorymaps:

Memory maps are the addressable area seen by a bus interface. This can be defined for each slave interface of a component. The memoryMaps element contains a unbounded list of memoryMap elements. The memoryMap element are referenced by the component’s slave interface.

  • addressBlock:

The addressBlock element describes a single, contiguous block of memory that is part of a memory map.

  • registers:

A register element describes a register inside an address block or register file.

  • businterfaces:

A businterface is a grouping of ports related to a function, typically a bus, defined by a bus definition and abstraction definition.

  • ports:

The ports elements defines an unbounded list of port elements. Each port element describes a single external port on the component. A port element contains a logical port information for a component.

  • views:

Views contains a list of all the views for this object. A component may have many different views. Each view can reference a component instantiation, a design instantiation, and a design configuration instantiation. A component instantiation may describe the source hardware module/entity with its pin interface. A design instantiation references an IP-XACT Design representation.

  • parameters:

Parameters describes any parameter that can be used to configure or hold information related to the component.

  • generators:

Generators are executable objects (e.g., scripts or binary programs) that may be integrated within a DE (referred to as internal) or provided separately as an executable (referred to as external).

  • file sets

File sets specifies groups of files and possibly their function for reference by other sections of this component description

  • Design documents

Design document contains XMLtags and attribute to describe the architecture of the design (e.g. – instantiation of an IP component inside componentInstances) and configurable parts (e.g.- configurable parameters inside configurableElementValues). Another important part is the interconnections describes how the IP’s inside a Design are connected to each other using bus interfaces or bridges.

  • Bus definition documents.

The bus definition document describes a bus type. It describes the signals in the bus interface and the constraints that apply to those signals. This includes signal names, direction, width, and usage. Bus definitions can also describe constrains on the use of that bus type, such as how many bus masters are allowed on each bus.
Abstraction Definition documents.
The abstractionDefinition element contains a list of logical ports that define a representation of the bus type to which it refers.

It is important to understand that IP-XACT XML standard is just a way to represent the structural and transport information of Design and IP. It is a set of plain text files. A good tool which understand this XML standard should be smart enough to import all the described information from a SoC design point of view.

IDesignSpec and SoC Enterprise tools of Agnisys generate all above-mentioned IP-XACT documents corresponding to a Register Specification in both IPXACT 2009 and 2014 editions.




IPXACT design structures are very complex, they may contain a long hierarchy chain of many Design and Component (IP or Bus) files. It is hard to manage their corresponding information like their addresses and remap addresses w.r.t to bus and interface interconnections.

Following is an example of a complex SoC design which IDS and SoCe can import easily and can create outputs mentioned above.




In the above example the System Bus (say AXI) is connected to multiple IP’s using different slave interfaces and with Another Bus (say AHB) with a bridge. IDesignSpec and SoCe can easily import these kinds of Design structures and the address remap information of IP’s w.r.t System Bus.

To import these kind of hierarchy user have to specify the Bus component in IDS using a property {ipxact.buscomp =”Bus component file path separated by comma in case of multiple files”} and to mention top design {ipxact.topdesign =”Path of top design document”}.

Following template shows how to mention these properties -






SoC Enterprise (SoCe) collects the metadata and converts it to the desired IP-XACT format. User can generate and also import IP-XACT to create its design in SoCe. In SoCe user can provide its information related to a design in following sheets -


  • General
  • Parameters
  • I/O Ports
  • Interfaces
  • Electrical
  • Physical
  • Enumeration
  • Views
  • IDS Template

Example of Electrical specification in SoCe:




Electrical information described in SoCe goes in vendor extensions of IP-XACT output:




The above IP-XACT can also be converted to graphical view and to other outputs:




SoCe can be used for IP-XACT packaging of a Design specification.

In summary, we have shown how simple and straightforward it is to create and import an IP-XACT description of a Register spec and Design (e.g.- Electrical, Physical and other information) using IDesignSpec and SoCe. In Electronic Design Industry Verification of a design is very important aspect and also it consumes a large amount of time. Under time to market pressure there may be chances that verification engineer may ignore bugs. By using these tools user can save his time by generating “Bug free” precompiled and synthesizable code of various HDL and HVL like Verilog, System Verilog and System-C etc.

By: Pankaj