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Newsletter:Paged Register In IDesignSpec

Paged Register In IDS

In computer operating systems, paging is a memory management scheme by which a computer stores and retrieves data from secondary storage for use in main memory. In this scheme, the operating system retrieves data from secondary storage in same-size blocks called pages.

Paging is an important part of virtual memory implementation in modern operating systems, using secondary storage to let programs exceed the size of available physical memory.

Paged registers are often used in embedded systems. Paged register is a set of registers sharing same physical address and another selector register is used to decide which out of them is actually accessed. The main usage of Paged register in embedded systems is for context switching.




In IDS we have two properties page_count and page_select for generating the page register. Property page_count shows the number of context registers and page_select for select line i.e selecting the context register.

Properties used in IDS for using Paged Register are

  • page_count – To Specify number of copies of a Paged/Mux register.
  • page_select – To specify the select signal for ‘n’ number of page registers, where ‘n’ is the number of page_count


Points to be noted

  • page_select and page_count, both properties should exist together to specify a Paged Register.
  • Field definition of all the paged registers will be same.
  • Only one register among the paged registers is accessible at a time, both from hardware or software side, based on the selector value.


RTL Generated through IDesignSpec

Following example shows that register ‘select’ whose field ‘Fld’ is used as a select line for the page register i.e select_Fld_q[1:0] value is used to select the page register.


always @(posedge clk)
      if (!reset_l)
               0 : Page_Fld_q_0 <= 32′d0;
               1 : Page_Fld_q_1 <= 32′d0;
               2 : Page_Fld_q_2 <= 32′d0;
               3 : Page_Fld_q_3 <= 32′d0;
if (Page_Fld_in_enb) // FLD : HW Write
                          0 : Page_Fld_q_0 <= Page_Fld_in;
                          1 : Page_Fld_q_1 <= Page_Fld_in;
                          2 : Page_Fld_q_2 <= Page_Fld_in;
                          3 : Page_Fld_q_3 <= Page_Fld_in;
            if (Page_wr_valid) // FLD : SW Write
                     0: Page_Fld_q_0 <= ( wr_data[31 : 0] & reg_enb[31 : 0] ) | (Page_Fld_q & (~reg_enb[31 : 0]));
                     1: Page_Fld_q_1 <= ( wr_data[31 : 0] & reg_enb[31 : 0] ) | (Page_Fld_q & (~reg_enb[31 : 0]));
                     2: Page_Fld_q_2 <= ( wr_data[31 : 0] & reg_enb[31 : 0] ) | (Page_Fld_q & (~reg_enb[31 : 0]));
                     3: Page_Fld_q_3 <= ( wr_data[31 : 0] & reg_enb[31 : 0] ) | (Page_Fld_q & (~reg_enb[31 : 0]));
            end // sw_write_close
end // always clk


UVM Model

In UVM-RAL Model we have to add the page register and its different context based on select register on different address map. In this example, we have two 32 bit registers, if the page register is specified at 0×4 location, than Page[0] is mapped at 0×04 and all other context registers i.e Page[1], Page[2] and Page[3] are outside the address space range specify in RTL.

For verification point of view IDS adds a task called pagedWrite for verifying the page register based on the value in select register.

default_map.add_reg( select, ‘h0, “RW“);

foreach (Page[Page_i])
                  default_map.add_reg(Page[Page_i],’h4 | Page_i << 3, “RW“);


select.add_hdl_path_slice(“select_Fld_q“, 0, 32);

foreach (regname[Page_i])
Page[Page_i].add_hdl_path_slice($sformatf(“Page_Fld_q_[%0d]“, Page_i), 0, 32);



task pagedWrite(uvm_reg_data_t count,uvm_reg_sequence parent_seq);
uvm_status_e status;
select.write(status, count, .path(UVM_FRONTDOOR), .map(default_map), .parent(parent_seq));
Page[count].write(status, 32′ha, .path(UVM_FRONTDOOR), .map(default_map), .parent(parent_seq));
Page[count].mirror(status,UVM_CHECK, .path(UVM_FRONTDOOR), .map(default_map), .parent(parent_seq));



We have shown how paged registers are described in IDesignSpec i.e IDSWord or IDSExcel, and their generated RTL and UVM Reg Model. UVM model is flexible enough to describe any quirky registers. We can change the model and the Register abstract layer according to verification needs.



By: Rohit