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Newsletter:Regalign in IDesignSpec

Regalign

IDesignSpec is an EDA tool used to generate RTL code and other outputs for a given specification about the registers in a variety of flavors such as IDS Batch, IDS Word, IDS Excel and IDS Calc.

With constantly improving technology and valuable feedback from our customers, Agnisys Engineering team constantly keep IdesignSpec a step ahead with the addition some new features.

One of the best feature that we are now supporting register with less and equal width (register size) than bus width(configure -> Bus Width) with backward compatibility register width only equal to bus width.

To do so, the user have to use property value pair {addressing = regalign}.

 

What is regalign?

The regalign is an address mapping technique, which states

        “The registers are packed so each register starting address is a multiple of its size(in Bytes). RegGroup are aligned according to individual register’s size”.

So from the definition of regalign,

         Register with width 8 bits can have starting address

0,1, 2, 3, ………. Where 0, 1, … are byte number

Register with width 16 bits will have starting address

0, 2, 4, …………. Where 0, 2, … are byte number

Register with width 32 bits will have starting address

0, 4, 8, …………. Where 0, 4, … are byte number

For Example:

If we have 3-registers of width 8, 8, 16 with bus width 32 then read and write operation will work as:

8-bit register [0:7] 8-bit register [8:15] 16-bit register [16:31]

All registers will be accessed in one clock cycle.

 

Template view:

https://www.agnisys.com/wp-content/uploads/2017/06/Capture1111111.png

RTL CODE :

:
:
Aligned offset and decode for Reg1
   assign Reg1_offset = block_offset+’h0;
   assign Reg1_decode = (address[Block1_address_width-1 : bus_bits] == Reg1_offset[Block1_address_width-1 : bus_bits] ) ? 1′b1 : 1′b0;
:
:
   always @(posedge clk)
:
:
Aligned software write for Reg1
          if (Reg1_wr_valid) // FLD : SW Write
                begin
                    Reg1_Fld_q <= ( wr_data[7 : 0] & reg_enb[7 : 0] ) | (Reg1_Fld_q & (~reg_enb[7 : 0]));
                end
             end // sw_write_close
            end end // always clk
:
:
   assign Reg1_rd_data = Reg1_rd_valid ? {Reg1_Fld_q} : 8′b00000000;
:
:
Aligned offset and decode for Reg2
   assign Reg2_offset = block_offset+’h1;
   assign Reg2_decode = (address[Block1_address_width-1 : bus_bits] == Reg2_offset[Block1_address_width-1 : bus_bits] ) ? 1′b1 : 1′b0;
:
:
   always @(posedge clk)
:
:
Aligned software write for Reg2
                 if (Reg2_wr_valid) // FLD : SW Write
                      begin
                           Reg2_Fld_q <= ( wr_data[15 : 8] & reg_enb[15 : 8] ) | (Reg2_Fld_q & (~reg_enb[15 : 8]));                        end
                end // sw_write_close
           end
  end // always clk
:
:
  assign Reg2_rd_data = Reg2_rd_valid ? {Reg2_Fld_q} : 8′b00000000;
:
:
Aligned offset and decode for Reg3
  assign Reg3_offset = block_offset+’h2;
  assign Reg3_decode = (address[Block1_address_width-1 : bus_bits] ==  Reg3_offset[Block1_address_width-1 : bus_bits] ) ? 1′b1 : 1′b0;
:
:
   always @(posedge clk)
:
:
Aligned software write for Reg3
                 if (Reg3_wr_valid) // FLD : SW Write
                     begin
                         Reg3_Fld_q <= ( wr_data[31 : 16] & reg_enb[31 : 16] ) | (Reg3_Fld_q & (~reg_enb[31 : 16]));
                      end
                 end // sw_write_close
             end
    end // always clk
:
:
Reading aligned data from all register
  assign Reg3_rd_data = Reg3_rd_valid ? {Reg3_Fld_q} : 16′b0000000000000000;
  assign rd_data = {24′h0,Reg1_rd_data} | {16′h0,Reg2_rd_data,8′h0} | {Reg3_rd_data,16′h0} ;
:
:

We have supported all other IDS property with register width less than and equal to bus width.

 

Summary:

The above discussion presents multiple registers being accessed only in single clock cycle, enabling faster RTL design. The property ‘addressing’ with value ‘regalign’ are supported by IDesignSpec version ‘6.6.16.0’ onwards. Now it is only supported in Verilog but to support in VHDL, UVM, ARV etc. is in our road map.

As we have done in the past, we request your feedback and will continue to work hard to improve IDesignSpec.

By: Tarun