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Newsletter:virtual register

VIRTUAL/ALTERNATE VIEW REGISTER

INTRODUCTION

We have often seen that Engineers require an “alternate view register”. Alternate view register basically consists of two registers at the same address location and based on the execution mode, one register is selected.

 

USAGE

Lets take an example:-

  • Design has a 32bit RW control register at block offset 0.
  • In a default “run” execution mode (modeA), the register is interpreted as having 4 8-bit fields. Each field controls the increment delta value for a corresponding counter. The increment delta value is added to 1 to get the actual increment value as the counter changes at every cycle during the run execution. Let’s call the fields {ctr3, ctr2,ctr1,ctr0} and the reset value is 0000_0000_0000_0000 which means the counters simply count by 1 (no additional increment value).
  • In an alternate run execution mode (modeB), the counters are not being used so the same register is used by the DUT for a different purpose. In this case, the register is interpreted as 2 16-bit fields. One field is the row address and the other is the target column address for a single memory instruction. Let’s call the alternate view fields {row,col}. The default in this mode could also be all 0s: 00000000_00000000.
  • If user run in modeA after writing 0000_0001_0000_0001 to the register, register will increment ctr0 and ctr2 by 2 and the other counters increment by 1.
  • Now if user wants to run in modeB in the same simulation and want to target row 1 and col 1.User do NOT have to re-write the register because it already has the value 00000001_00000001. User should also be able to write in one mode and read the value back in the other mode so that he or she can see how the value will be viewed in the alternate mode.
  • When user randomize or write a value in a particular mode, he would be able to refer constraints and relevant fields based on the mode.
  • User want to be able to display the register showing the fields based on a mode. Same for writing, reading, getting fields, randomizing… all should be based on the current mode that is applied to the regmodel.

 

LOGICAL VIEW

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IMPLEMENTATION

The solution of Alternate view register is based on virtual registers and modelling the physical register as a memory.We have mapped two virtual registers with single physical memory based on a mode variable.The mode variable can be set and read from the config_db.

Uvm model of above example:-

Counter is a regmodel of register in execution modeA and col_row is a register of modeB.

….

// Function : build
virtual function void build();
//create
counter = Block1_vreg1::type_id::create(“counter“);
col_row = Block1_vreg2::type_id::create(“col_row“);
mem = Block1_Reg1::type_id::create(“mem”);
//config
mem.configure(this,”inst.Stack”);
counter.configure(this, null,1);
col_row.configure(this, null,1);

….

While in the simulation, based on the execution mode, the virtual register is implemented.

In all the case, the transactions in the virtual register is basically on the memory.

….
If (mem != null) begin
If (mode==A) begin
vregs=blk.get_vreg_by_name(“counter”);
end
else begin
vregs= blk.get_vreg_by_name(“Col_row”);
end
vregs.implement(1,mem);
end
….

CONCLUSION

UVM model is flexible enough to describe any quirky registers. We can change the model and the Register abstract layer according to verification needs. The inclusion of the Extension Object for register methods provides a flexible way to communicate any type of data across the UVM RAL. We have shown how to create UVM reg model for alternate view registers.

 

By: Kirti