IDesignSpec incorporates SystemRDL functionalities

SystemRDL v2.0
SystemRDL is a language used for the design and delivery of intellectual property (IP) products in design systems. SystemRDL semantics supports an entire life-cycle of registers right from the specification, model generation, and design verification, to maintenance and documentation. Registers are not just limited to traditional configuration but can also refer to register arrays and memory.

IDesignSpec incorporates SystemRDL v2.0 functionalities
IDesignSpec now supports SystemRDL v2.0 functionalities by taking input SystemRDL v2.0 file and generating output SystemRDL v2.0 file from multiple inputs which IDesignSpec supports. Features such as:

  •        Constraints
  •        Structures
  •        Memory
  •        Software access
  •        Parameters
  •        Enum
  •        HDL Path

Are now supported in SystemRDL 2.0 format.

Listed below are the new features implemented in SystemRDL v2.0 with detailed examples:

Parameterized documentation can now be created. The parameters can be resolved at the documentation level.

For example:

reg myReg #(unsigned longint SIZE = 32, boolean REGISTERED = true) {

regwidth = SIZE;

registered = REGISTERED;

field {} data[SIZE];

};

addrmap myAmap {

myReg reg32;

myReg reg32_arr[8];

myReg #(.SIZE(16)) reg16;

myReg #(.SIZE(8), .REGISTERED(false)) reg8;

};

Various specifications of the register can be parameterized and overridden at the time of instantiation. To define Verilog-style parameters in SystemRDL, parameter definitions shall be specified after the component’s name. parameter_definition is defined as follows.

parameter_type parameter_name [= parameter_value]

Structures are supported at the documentation level:

For example:

struct my_struct {

string foo ;

string desc1;

} ;

addrmap top {

regfile some_regfile #( my_struct arg ) {

reg {

desc = arg.foo ;

field {

desc = arg.desc1;

} a ;

} regA ;

} ;

some_regfile #(.arg( my_struct'{ foo: “reg desc”, desc1:”field desc” })) regFA ;

some_regfile #(.arg( my_struct'{ foo: “reg2 desc”, desc1:”field2 desc” })) reggrp2 ;

Structs enable the creation of structured properties for more complex extension of component types.

Expressions are supported with arithmetic operations such as | |, &&, !  etc.

For example:

reg some_reg #(boolean BYTEENB = false) {

ext_byte_enb = !BYTEENB ; //expression

field {} b;

b -> ispresent = false ;

field { ispresent = false ; } d ;

} ;

some_reg #(.BYTEENB(true)) reserved_reg ;

some_reg partially_reserved_reg ;

some_reg not_reserved_reg ;

not_reserved_reg.b -> ext_byte_enb = true ;

not_reserved_reg.d -> ext_byte_enb = true ;

Values can be post assigned during declaration and can also be given in the form of an array:

For example:

addrmap block_def {

hdl_path = “int_block” ;

reg {

hdl_path = `{ “ext_hdl_path”, “externl_reg” } ;

field {

hdl_path_gate = `{ “field1” } ;

} f1 ;

} external_reg ;

reg {

hdl_path = “int_reg” ;

field {

hdl_path_gate = `{ “field1” } ;

} f1 ;

} internal_reg ;

} ;

addrmap top {

hdl_path = “TOP” ;

block_def int_block0 ;

int_block0 -> hdl_path = “int0” ;

block_def int_block1 ;

int_block1 -> hdl_path = “int1” ;

};

Memory can be defined using the keyword ‘mem’ as shown below:

For example:

mem fixed_mem #( unsigned longint  word_size = 32, //mem keyword

unsigned longint  memory_size = word_size * 4096) {

mementries = memory_size / word_size ;     //complex expressions supported

memwidth = word_size ;

} ;

  1. Different data types are supported such as unsigned long int, Boolean, string etc.
  2. Constraints are now supported in systemRDL 2.0 format.

A constraint is a value-based condition on one or more components; e.g., constraint-driven test generation allows users to automatically generate tests for functional verification. Constraints can be instantiated within all structural components.

addrmap Admap {

name = “Admap Address Map”;

reg Reg21 {

   regwidth = 32;

  field {

    constraint { this <=10; } Reg21_F1_constraint;                                                                                                                               

    hw = rw;

    sw = rw;

  } F1[16:0] = 17’h0;

};

reg Reg32 {

   regwidth = 8;

  field {

    constraint { this == 8; } Reg32_F1_constraint;      

    hw = rw;

    sw = rw;

    onread=r;

    onwrite=w;

  } F1[6:0] = 7’h0;

};

};

Summary:

IDesignSpec enables IP/SoC design teams to create code files from the register specification, saving time and producing consistent, quality results. IDesignSpec (IDS) generates System RDL registers right from the user’s specification. Therefore, the user can create various IDesignSpec outputs from the standard input SystemRDL file.