ASVV™ – A complete Integrated Software for SOC/IP teams who aim to cut down the verification and validation time. ASVV automatically generates UVM and C sequences which exhaustively test the memories and register maps. ASVV also provides a way to generate custom tests for boards, UVM and UVM-C based environments through a common specification. It provides a complete solution for firmware engineers to write and debug the device drivers and application software.

Automated Test Generation:

  • Positive and negative tests for testing various register access types for UVM based environments.
  • Tests to check the functionality of special registers like Lock Register, Page Register and Indirect Register which provide 100% coverage for UVM based environments.
  • C and UVM tests to verify rw, wo and ro access of registers.
  • C and UVM tests to verify the special registers like shadow, alias etc.

Custom Test Generation:

  • Generates user defined functional tests in order to verify the functional behaviour of a block.
  • Configuration sequences can be used for testing as well as for device driver development.
  • Single specification to generate tests for multiple platforms like UVM, UVM/C and boards.
  • Python and Excel based flow to write the test specification.

Additional Features:

ASVV not only generates automated and custom tests but also generates various verification environments for running the same.

ASVV generates three kind of environments: –

  • UVM environment for verification.
  • UVM-C based SOC verification environment.
  • Co-verification environment.

UVM environment for IP verification:

  • Generates all essential UVM components along with integrated RAL model.
  • Generates UVM agents based on the configuration settings like axi, ahb etc.
  • By default, memory map is integrated for testing the generated rtl and sequences.
  • Automated and custom generated tests get automatically integrated.
  • It can be used as starting point for IP verification.

UVM-C based SOC verification environment:

  • Generates UVM-C based environment which can run both C and UVM tests.
  • RISC-V based SweRV Core EH1 rtl is integrated for running the C programmes.
  • A synchronizer component is also generated which provides synchronization between C and UVM tests.
  • C programs are used to configure the IP blocks whereas UVM tests can be used to drive the ports and extra logic.
  • Capable of handling interrupts and their ISR routines.
  • Can be used as a starting point for developing a SOC verification environment.
  • Can be used to test the connection b/w various IP blocks.
  • Can be used to develop, debug the device drivers or software for various IP blocks.

 Co-Verification environment:

  • QEMU and UVM based environment capable of running C and UVM tests.
  • QEMU is used for emulating the processor behaviour.
  • Can be used to develop or debug the devices drivers for IP blocks.