Register for the Webinar:
The Complete Solution for Register Specification, Design and Verification
Semiconductor design is challenging during the best of situations. The amount of code that design and verification teams must create combined with the complexity of the IP blocks that they must integrate makes their projects very difficult and the risks of success are significant.
To reduce the time and risks of chip design projects, teams are adopting tools that automatically generate code and tests for design registers. Learn how by attending this webinar.
When: Wednesday, November 12, 1:00 to 2:00 PM Eastern Standard Time
Who should attend: Spec Writers, Architects, Designers, Verification Engineers, Firmware Developers
What will you see:
- how to develop correct-by-construction register definitions from a single register specification:
- auto-generation a range of outputs from a single specification
- accepting Word, Excel, SystemRDL, XML, IP-XACT, CSV, Framemaker, RALF, and custom inputs
- generating Verilog, VHDL or SV RTL, UVM, C/C++ Headers, RAL, XML, IP-XACT, SystemRDL, custom outputs (via Tcl), PDF, HTML
- support for all popular bus types like AXI, AHB, APB, AVALON etc.
- advanced topics such as parameterization, multiple bus domains, channelization, constraints,coverage, backdoor access, low-power RTL and special registers
- auto generation of the “Complete” verification environment, over and above UVM including bus agents, virtual sequencers, RTL, associated tests, and an annotated verification plan