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What Every Engineer Should Know About SoC Register Generation

What Every Engineer Should Know About SoC Register Generation

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Register Generation is a Must-Have Capability

Today's SoC designs contain several thousands of registers and memory map elements. The design team must, from the architecture, create the register and memory map documentation and then map each element to the design code and design verification code for each and every register and memory map element. To compound this challenge, each bit and its property involve significant time and complexity to ensure the coding is correct.

Registers and memory elements constitute a significant percentage of today’s complex SoC designs. On-chip registers define the software interface to the semiconductor and usually represent the largest portion of the device specification and programmer's guide. The numbers of registers continue to increase as SoC design complexity grows, escalating the number of registers compounding documentation, implementation and maintenance challenges. What's more, changing specifications during the design cycle necessitates repeated updates to design, test-bench, and register/memory test cases and documentation. 

 This process repeats itself many times over the course of the project. Bugs are only one source of change though. Change requests may also come in at any stage of the design cycle requiring the specification to change and all downstream code to be modified to stay synchronized with the specification.

Manual methods for register generation create multiple sources of error

Register Generation from SpecificationRegister definition starts with an architect scoping out a specification. Armed with a completed specification, the hardware engineer, software engineer, and verification engineers can begin coding each of their different views of the registers described in the functional specification. Once the initial design is in place, verification and software engineers can start running tests. Anytime a bug is discovered the specification must change, and all the subsequent outputs must follow. Depending on the nature of the update, the change has to be manually applied to all the existing design representations. Similarly, problems found at any stage of the development process, have to be fixed in all the design representations. This process relies entirely on good communication between various design teams. These teams are often working in different settings, and most likely are geographically distributed as well. This makes this process tedious and is error-prone with negative project schedule and quality consequences.

What is all too common in these instances of constant change, due to schedule priorities, the designer may change his code but not update the documentation.  Any attempt to manually manage these components impairs productivity and increases the probability of introducing errors in the semiconductor design, embedded software and design verification process.

The new approach to register generation that improves productivity and eliminates errors

By starting from a single source, represented in a high-level register and memory modeling language like SystemRDL, IP-XACT or for simpler designs, a Word or Excel file, and auto-generating each down-stream representation for documentation, design and verification, the project complexity decreases and the automation eliminates error sources. 

SystemRDL, IP-XACT, Excel or Word-based specification sources combined with automation provides a single point to make specification changes.  From any of these sources, commercial software can drive automated generation of synthesizable RTL code for the design, C header files for firmware, SV/UVM code for verification, Documentation and other needed outputs for the project.  Although engineers can use SystemRDL, there is advantage in keeping the register specification close to the remaining hardware design specification. The advantage is obvious - everything pertaining to the hardware is in one place.

The bottom line for register generation

The unified register and memory map environment offered by automated tools significantly improve the efficiency of all development teams, especially when they have to react to a specification change. What’s more, automation virtually eliminates risk of consistency mismatch between the different environments, each of which depends on each matching the other completely. This approach drastically increases the overall quality of the product and eliminates schedule delays.

20 advantages for automating your ASIC or FPGA transition from Specification to Design

Download IDesignSpec for Register Generation for SoCs

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