A Standard way to build IPs and SoC using IDesignSpec and IP-XACT

The two biggest challenge of today’s complex design are IP-Integration and Verification, and we would like to address solution scoping the discussion to the register implementation which is the core competency of Agnisys. Few year back with the rise of ecosystem of multiple IP provider there was a great need of describing the IP using a standard format to maintain consistency of the information.

The goals of the IP-XACT standard are:

  • To ensure delivery of compatible component descriptions from multiple component vendors,
  • To enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments)
  • To describe configurable components using metadata,
  • To enable the provision of EDA vendor-neutral scripts for component creation and configuration (generators, configurators)

IP-XACT standard is followed by leading companies for defining and describing: components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (w3c) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.

Focusing on Register: As we know implementing registers is not difficult but it is a monotonous task as often changes are introduced late in the design cycle which creates issues such as – Register location ambiguity, Register type definition, Register definition/bit fields, Register implementation. The core philosophy of using single source file for implementing registers by using correct by construction approach with added advantage of reusing existing data.

IDesignSpec beautifully complement the completeness of IP-XACT to capture the register information and generate the verified implementation in various formats such as Synthesizable RTL, Synthesizable SystemVerilog, UVM Register Model and verification environment, C/C++ header files, documentation and for reusing register details SystemRDL, and XML files. The uniqueness of IDesignSpec is to use a single source file to generate integrated outputs, which reduce risk of ambiguous functionality.

IP-XACT code generated by IDesignSpec –

<spirit:component xmlns:ids="https://www.agnisys.com/"
   xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
   xmlns:xrsl="https://www.agnisys.com/">
   <spirit:vendor>Agnisys_Inc.</spirit:vendor>
   <spirit:library>Agnisys_Inc.</spirit:library>
   <spirit:name>RGU_csv_model</spirit:name>
   <spirit:version>1.0</spirit:version>
   <spirit:memoryMaps>
      <!--//chip:RGU_csv-->
      <spirit:memoryMap>
         <spirit:name>RGU_csv</spirit:name>
         <spirit:addressBlock>
            <spirit:name>ambaAPB</spirit:name>
            <spirit:description/>
            <!-- // block : ambaAPB  -->
            <spirit:baseAddress>0x00</spirit:baseAddress>
            <spirit:range>72</spirit:range>
            <spirit:width>32</spirit:width>
            <spirit:register>
               <spirit:name>reset0Delay</spirit:name>
               <spirit:description>"Delay value for reset 0</spirit:description>
               <spirit:addressOffset>0x0</spirit:addressOffset>
               <spirit:size>32</spirit:size>
               <spirit:volatile>false</spirit:volatile>
               <spirit:reset>

Agnisys works with a variety of customers and we come across use cases that are beyond the scope of IP-XACT. Fortunately we can still describe the beyond the special features in IP-XACT using Vendor Extensions (VE). Features like Alias, Interrupt, counter, Paged, trigger buffer register, custom connection, UVM properties etc. have been implemented using VE.

IDesignSpec Key Benefits with IP-XACT – Improves Design Team Performance 

  • Not only can IDesignSpec read in IP-XACT files, you can also generate them from Word, Excel and other simpler, easy to specify formats
  • Automatically verify all addressable registers in the design to ensure generated register code is correct
  • Create synthesizable code for registers for design teams and keep them synchronized with requirements
  • Faster and more accurate Device Driver, Firmware and application software development eliminates errors in communication of interfaces between functional teams
  • Automatically create product documentation for customers and technical publications
  • Improves productivity of engineers and quality of results
  • Supports Architecture, Design, Verification, Diagnostics, Firmware, Application Software and Documentation teams
  • Allow design teams to reuse the existing data

IDesignSpec Availability: IDesignSpec is available as a plug-in for popular editors that are commonly used to document registers (Microsoft Word, Microsoft Excel and LibreOffice) and as a command line utility for Windows, Linux and MAC platforms.

Contact us for details – sales@agnisys.com

Ref- https://en.wikipedia.org/wiki/IP-XACT
       http://accellera.org/activities/working-groups/ip-xact/

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By Comments off March 22, 2022