+1 855-VERIFYY
+

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

By: | Tags: , , , | Comments: 0

System on Chip Design Challenges - The Highlight of DAC Day 2

It was a very busy day for Agnisys on the second day of the Design Automation Conference. On day two, we learned how much our products address System on Chip design challenges.  

Gary Smith system on chip design challengesGary Smith visited our booth and told us how strategic our tools were because of the increasing System on Chip design challenges and with FPGAs too. Gary is an EDA visionary and we were proud that he identified our set of products as critically important for the semiconductor industry and to address these challenges.  

Gary, if you read this post, we LOVE your red sox!  Perhaps your a Boston baseball fan.  

Many engineers came by and discussed the increasing difficulty in the SoC design and verification space, especially managing register definition and generating the associated code.  What's more, they discussed the problems they experience when specs change and they need to keep the registers and memory maps in synch between the specification, the design, the Design Verification code and documentation.  

One senior asic designer at a fortune  500 company talked about several groups within the company  having their own unique flow related to registers. Some liked to use textual input for describing registers,  others wanted a more expressive way to look at the register data, in a word document,  yet others wanted to conform to ip-xact. His challenge was how to satisfy all groups and ensure that everyone was able to share data and generate same outputs.  Of course we educated him about IDesignSpec and its ability to address each of his group's need.  

Another user that visited had constraints on his register bits and he did not know how to address that requirement as far as design verification coverage was concerned.  His issue was that when he constrained his register bits the coverage dropped significantly which was obviously not correct.  He was thrilled once he learned that IDesignSpec addresses this need automatically.  

It was interesting to see several Universal Verification Methodology trainers really liking DVinsight. Cliff Cummings and Stuart Sutherland, who collaborate and compete on UVM training were unanimous in the usefulness of DVinsight for people new to UVM. One verification architect disagreed and said it is useful not only for new users but experienced users too, which is our point exactly.  See our post yesterday about the adoption rate of Universal Verification Methodology.

At the end of the day I participated in birds-of-a-feather for portable stimulus generation which is at the proposed working group stage following the new Accellera process.  We look forward to day 3 with great anticipation!  

20 advantages for automating your ASIC or FPGA transition from Specification to Design

Leave a Reply