DAC | Agnisys

2017 June

Spotlight Is ON

● Bigger regwidth registers in IDesignSpec

Thank you for reading the June Agnisys Spotlight. In this issue we review several enhancements in design specification using IDesignSpec. Starting with FIFOs their sync and async versions, help Software/Hardware to communicate with each other. In order to reuse IPs, it is possible that there is a difference in size of the registers and the bus width used to access them. Next, alignment of the address map components are important for proper access. We also discuss two complex, yet popular type of registers – the paged register and virtual register. From now on, if user contributes an articles on how user uses IDesignSpec we offer a chance to win $100 Amazon Gift card and other goodies. If yours is the only contributed article we think you will have a high chance of winning ☺

– Anupam Bakshi, CEO, Agnisys, Inc.

“Special FIFO Register”

FIFO is an acronym for First In First Out. It is the queue used to store data and use it via two systems to communicate with each other. In FIFO whichever data is filled first in the queue, the same data is read from other system.

Data Communication in between two systems need the storage elements. Here the FIFO lies in the communication systems. Depending on the requirements, the FIFO is made up of shift register or a memory element…Read more

Bigger regwidth registers in IDesignSpec

IDesignSpec is an EDA tool that solves most of the designer’s problems, in minutes rather than hours. In every release, we work to make some improvements and enhancements to make our tool the World’s best. In this release, we did something that was asked by our customers to support registers having width greater than the selected bus width. Although, supporting this particular feature required a lot of research and was a brainstorming exercise for our engineering team.

For quite a sometime, we had been putting off the implementation of register width greater than bus width as were searching for the best algorithm to support bigger regwidth registers that can take lesser time while reading and writing from the bus– for all combinations of registers, fields and busses. When an IP is reused, Read more…

Regalign in IDesignSpec

IDesignSpec is an EDA tool used to generate RTL code and other outputs for a given specification about the registers in a variety of flavors such as IDS Batch, IDS Word, IDS Excel and IDS Calc.

With constantly improving technology and valuable feedback from our customers, Agnisys Engineering team constantly keep IdesignSpec a step ahead with the addition of some new features.

One of the best feature that we are now supporting is register with less and equal width (register size) than bus width(configure -> Bus Width) with backward compatibility register width only equal to bus width. To do so, the user have to use property value pair {addressing = regalign} Read more…

Paged Register In IDesignSpec

In computer operating systems, paging is a memory management scheme by which a computer stores and retrieves data from secondary storage for use in main memory. In this scheme, the operating system retrieves data from secondary storage in same-size blocks called pages.

Paging is an important part of virtual memory implementation in modern operating systems, using secondary storage to let programs exceed the size of available physical memory.

Paged registers are often used in embedded systems. Paged register is a set of registers sharing same physical address and another selector register is used to decide which out of them is actually accessed. The main usage of Paged register in embedded systems is for context switching.Read more…

Virtual/alternate view register

We have often seen that Engineers require an “alternate view register”. Alternate view register basically consists of two registers at the same address location and based on the execution mode, one register is selected.

Lets take an example:-