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2017 Dec

Spotlight Is ON

Agnisys wishes you a joyful and prosperous 2018. We are delighted to introduce the last edition of the Agnisys Spotlight Newsletter in 2017.

In this issue, we review several enhancements in design specification using IDesignSpec – like capability of handling register aliasing in two different ways. IDS now enables users to customize and create their own new outputs using Velocity templates. The 10-bit I2C Serial interface is now supported.
Agnisys has created a new Integrated Development Environment (IDE) – IDS NextGen, which enables users to capture the specification of IP and SoC using Behavior-Driven Development (BDD) methodology for IP/SoC

We hope you find these articles useful. And as always, we welcome your suggestions and improvements.

– Anupam Bakshi, CEO, Agnisys, Inc.

IDesignSpec NextGen™

Agnisys has created a new Integrated Development Environment (IDE), which enables users to capture the specification of IP and SoC. The new IDE has no dependency on other editors and no dependency on a particular operating system. IDesignSpec NextGen™ (IDS-NG) is a new technology with Window, linux and Mac based GUI application.
IDS-NG is a purposefully built tool from the ground up for the entire IP/SoC team to capture their design specifications and automatically generate code from it.Read more

Register Aliasing

Register design and implementation is one of the most important parts of today’s hardware and IC designs. Registers contain the configuration, control setting and status of the hardware and are the basis of the hardware and software interface.

In hardware design, register aliasing describes a situation in which a register location in the hardware design can be accessed through additional symbolic names and addresses. The fields in aliased registers have different access based on the address used.Read more

Format property implementation for IDS/ISS

Normally only integers are represented in fixed point numbers. This implicitly means that the decimal point is at the right most corner of a number. Also, integers can be signed (2’s complement) or unsigned. However, in Math intensive applications, fixed point numbers can also be used to represent real numbers. In this case the decimal point moves towards left of the number. Read more

I2C Supported in IDS

IDesignSpec now supports the Serial interface via the I2C bus protocol. Various operating modes are implemented.

It contains the I2C-bus data transfer, handshaking and bus arbitration schemes. I2C widget is implemented for 7 bit addressing mode as user will specify the address of the device as slave address. Which will be user specified. 8-bit register address is supported for read and write the data. The I2C widget will take data into I2C format from I2c Master device and converts it to proprietary interface. Read more…

Apache Velocity Template

IDesignSpec (IDS) introduces its new feature which enable users to customize and create their own outputs using Velocity template- main benefit of using Apache Velocity Template. It enables user to create fast and personalized outputs.

Our Velocity template is based on a very simple architecture with two components – a data model and the template. This data model is basically the input IDesignSpec file which describes the design specification. Input file can be of any format which is supported by IDesignSpec example: SystemRDL, Read more…

Repeat on Memory

A memory is a storage with contiguous address locations. As the increasing integration density of various IPs into the SoC, the memory system becomes a dominant role to determine the final performance, area, and power consumption of SoC. Different memory templates are required in IDS to have different interferences of memory currently, but if the size of memory is same and different interferences with different ports are required then ‘repeat’ property on memory template can be used.Read more…

Upcoming events:

DVCON 2018 | San Jose, CA | Feb 26 – Mar 1, 2018

DAC 2018 | San Francisco, CA | June 24-28, 2018

Recent Blogs:

A pragmatic approach towards transformation – Consolidation in Semiconductor Industry

Different flows for UVM Register Generation