2017 Oct
Spotlight Is ON
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● Agnisys now supports Duolog format ● SPI:(Serial Peripheral Interface) |
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Happy Diwali! Thank you for visiting October Agnisys Spotlight. In this issue we review several enhancements in design specification using IDesignSpec – like support for ex-Duolog customers. We also bring problems of using registers that users reported and our solutions like – Counting Interrupts. We are now supporting both I2C and SPI serial busses with IDesignSpec. One of the big problems that users have with gate level simulation is specifying the hdl_path for Gates which we have solved with a new property. Last but not the least, we talk about parameterization in IDS and how you can now use an array of parameters for initializing array of registers or reg-groups. We hope you find these articles useful. And as always we welcome your suggestions and improvements – that not only keeps us going, it has over the years, made our products more robust, comprehensive and versatile. – Anupam Bakshi, CEO, Agnisys, Inc. |
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Agnisys now supports Duolog format The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader and SystemC. The outputs are generated similar to both Duolog as well as IDS formats. Current users of Duolog can evaluate the new outputs and eventually get the benefits of Agnisys with faster RTL and more versatile UVM. |
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Count Interrupts Designs often have a need to count the number of times an interrupt occurred. To count the interrupt on the line, we use set of properties {counter.sw.wr.enb=regname.fieldname,intr; counter.sw. wr=incr,1}.Read more |
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SPI:(Serial Peripheral Interface) The SPI bus is a synchronous serial communication interface specification used for short distance communication. In order to synchronize SPI bus with IDS proprietary bus, information will be taken from the master/user through the data line (MOSI). So, for a read or write cycle, first 8 bits will be the IDS instruction set, next 8 bits will be the address of the register to which it wants to communicate and next will be the data bits which depend on the bus width of the proprietary bus.Read more… |
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I2C Supported in IDS IDesignSpec now supports the Serial interface via the I2C bus protocol. Various operating modes are implemented. It contains the I2C-bus data transfer, handshaking and bus arbitration schemes. I2C widget is implemented for 7 bit addressing mode as user will specify the address of the device as slave address. Which will be user specified. 8-bit register address is supported for read and write the data. The I2C widget will take data into I2C format from I2c Master device and converts it to proprietary interface. Read more… |
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HDL PATH for Gate Level Simulation In UVM, the register abstraction layer describes the register and memory behavior of the Design Under Test (DUT). An “hdl_path” is specified for the RTL storage of the registers. When the Gate level simulation is performed, the corresponding hdl_path properties need to be added. We can read/write the register or memory with two methods:
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Parameterization in IDS In IDesignSpec, parameters are constants that can be changed from the simulation command line. Typically, parameters are used for constants like number of clients, number of ports, inclusion/exclusion of blocks etc. User is now able to specify parameters and defines in the define table typically at the top of the document and use these as macros to assign values to all properties. User can pass array using parameter. The property sv_param is applied on the top-level module for SV header outputs. It converts the `define to the parameter inside the package.Read more Upcoming events: DVCON 2018 | San Jose, CA | Feb 26 – Mar 1, 2018 DAC 2018 | San Francisco, CA | June 24-28, 2018 Recent Blogs: Different flows for UVM Register Generation Growth in Design Verification Consulting Services Addressing MAC and Linux GUI requirements for Register and Memory Map Specifications |