In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world
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By Louie De Luna, Agnisys Chief Product Evangelist As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to
Read moreIdentifying the challenges in moving from a static spec to a live one.
We all want our creations to transcend time. Our products, our
Read moreSomewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity.
As the saying goes, the faint of heart
Read morePublished on 05-19-2013 07:30 PM in Semiwiki It goes without saying that registers play a vital role in designing any ASIC, FPGA, SoC or System. In today’s world, while designing SoC
Read moreSo the cat is out of the bag. We are working on an assertion tool. This DVCon we turned quite a few heads when we announced our new assertion
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